Showing papers on "Silicon on insulator published in 1987"

Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance

Abstract: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.

Introduction to microelectronic fabrication

Abstract: (NOTE: Each chapter concludes with Summary, References, and Problems) Preface 1 An Overview of Microelectronic Fabrication A Historical Perspective An Overview of Monolithic Fabrication Processes and Structures Metal-Oxide-Semiconductor (MOS) Processes Basic Bipolar Processing Safety 2 Lithography The Photolithographic Process Etching Techniques Photomask Fabrication Exposure Systems Exposure Sources Optical and Electron Microscopy Further Reading 3 Thermal Oxidation of Silicon The Oxidation Process Modeling Oxidation Factors Influencing Oxidation Rate Dopant Redistribution During Oxidation Masking Properties of Silicon Dioxide Technology of Oxidation Oxide Quality Selective Oxidation and Shallow Trench Formation Oxide Thickness Characterization Process Simulation 4 Diffusion The Diffusion Process Mathematical Model for Diffusion The Diffusion Coefficient Successive Diffusions Solid-Solubility Limits Junction Formation and Characterization Sheet Resistance Generation-Depth and Impurity Profile Measurement Diffusion Simulation Diffusion Systems Gettering 5 Ion Implantation Implantation Technology Mathematical Model for Ion Implantation Selective Implantation Junction Depth and Sheet Resistance Channeling, Lattice Damage, and Annealing Shallow Implantation Source Listing 6 Film Deposition Evaporation Sputtering Chemical Vapor Deposition Epitaxy Further Reading 7 Interconnections and Contacts Interconnections in Integrated Circuits Metal Interconnections and Contact Technology Diffused Interconnections Polysilicon Interconnections and Buried Contacts Silicides and Multilayer-Contact Technology The Liftoff Process Multilevel Metallization Copper Interconnects and Damascene Processes Further Reading 8 Packaging and Yield Testing Wafer Thinning and Die Separation Die Attachment Wire Bonding Packages Flip-Chip and Tape-Automated-Bonding Processes Yield Further Reading 9 MOS Process Integration Basic MOS Device Considerations MOS Transistor Layout and Design Rules Complementary MOS (CMOS) Technology Silicon on Insulator 10 Bipolar Process Integration The Junction-Isolated Structure Current Gain Transit Time Basewidth Breakdown Voltages Other Elements in SBC Technology Layout Considerations Advanced Bipolar Structures Other Bipolar Isolation Techniques BICMOS 11 Processes for Microelectromechanical Systems-MEMS Mechanical Properties of Silicon Bulk Micromachining Silicon Etchants Surface Micromachining High-Aspect-Ratio Micromachining: The LIGA Molding Process Silicon Wafer Bonding IC Process Compatibility Answers to Selected Problems Index

Porosity and Pore Size Distributions of Porous Silicon Layers

Abstract: Porosities of porous silicon layers formed on different types of substrates and under different experimental conditions are compared with and related to the pore size distribution determined by gas adsorption experiments. Results show that porous layers formed on lightly P-doped silicon exhibit a network of very narrow pores, of radii less than 2 nm. Porous films formed on heavily doped silicon present larger radii, ranging between 2 and 9 nm according to the experimental conditions. Larger porosities and larger pore sizes are obtained by increasing the forming current density or by decreasing the HF concentration. Heavily P-doped porous silicon layers are homogeneous in depth and generally present a quite sharp pore size distribution. With heavily N-doped silicon, an increase in porosity with increasing thickness is found, which corresponds to an increase in pore size, leading to a broadening of size distributions. This porosity gradient is attributed to a chemical dissolution of the layer occurring during anodization. In addition, a strong dependence of porosity with small variations in doping level is found. Porous silicon is a material obtained by anodic oxidation of monocrystalline silicon in concentrated hydrofluoric acid solutions. Several papers (1-4) have shown that this material is one of the promising candidates for use in silicon on insulator (SOI) structures in integrated circuit technology. In all the proposed applications, the oxidation properties of porous silicon are used to obtain thick insulating layers of silica in relatively short periods of time. The properties of the material are very dependent on the type and resistivity of the original silicon substrate and on the electrochemical parameters used during the anodization processes. Porous silicon is often characterized by its porosity, mainly due to the existence of a so-called optimal porosity of about 56%, for which good silicon dioxides are obtained with minimum strains and volume expansion (5), which is necessary to obtain fully oxidized structures. However, porosity values alone are not enough to characterize the material as quite different properties can be obtained for materials of the same porosity if the substrate resistivity and preparation conditions are properly chosen. Other parameters to be considered when a better characterization of porous structures is required are pore size and pore size distribution. Both porosity and pore size determine altogether the size of the silicon walls in the porous material, so that properties like crystalline quality (6), optical response (7), thermal behavior (8), and oxidation mechanism (9) are very dependent on both porosity and pore size. It has been shown in a previous paper (10) that it was possible using gas adsorption techniques to determine accurately the pore size and pore distribution of radii in the porous silicon layers. That work was limited to porous silicon layers prepared on (111) heavily P-doped substrates. The aim of the present work is to study (100) substrates and investigate other kinds of resistivity and different electrochemical preparation conditions. Experimental

An SOI voltage-controlled bipolar-MOS device

Abstract: This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Abstract: Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.

Method for removing impurities existing in semiconductor substrate

Abstract: A large quantity of oxygen (1018 cm-3) is dissolved in a semiconductor, for example, a silicon crystal substrate. In particular, in the SOI technology for forming a buried oxide film in silicon by oxygen ion implantation, a large quantity of oxygen (up to 1020 cm-3) is left over in the silicon top layer. Such oxygen in the silicon becomes fine precipitates (defects) by the subsequent heat treatment step. Disclosed is, hence, a method for obtaining a semiconductor substrate of high quality by removing impurities by implanting ions containing light element (for example, hydrogen) before heat treatment.

Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor

Abstract: A method of forming a high quality silicon on insulator semiconductor device using wafer bonding. The annealing time for the wafer bonding process is substantially reduced through the use of a rapid thermal annealer, thereby resulting in minimizing the redistribution of the doping concentration resulting from the annealing process.

Metal-insulator-semiconductor capacitor formed on silicon carbide

Abstract: The invention comprises a metal-oxide-semiconductor (MOS) capacitor formed on silicon carbide. By utilizing new techniques for obtaining single crystals and monocrystalline thin films of silicon carbide, and by positioning the ohmic contact and the metal contact on a common side of the silicon carbide semiconductor portion, devices are obtained which are commercially viable and which demonstrate reduced series resistance, lesser leakage current and greater capacitance than have previous devices formed on silicon carbide.

Semiconductor memory device

Abstract: PURPOSE:To provide a semiconductor memory device integrated with a high density by a method wherein a capacitor is provided in a groove formed in a semiconductor substrate and a transistor is provided on an insulating layer formed selectively on the semiconductor substrate and the capacitor and the adjoining transistor are connected by the region of the semiconductor substrate adjacent to the side wall of the insulating layer. CONSTITUTION:An N type diffused region, which is to be one of the electrodes of a capacitor is connected to the source region of a TFT by single crystal 4 and the connection is secured. Moreover, the connection can be formed by a self-alignment manner with a part of a mask pattern for a trench and a part of a mask pattern for a transistor overlapping each other. As a transistor provided on an SiO2 layer 3 has an SOI structure, a space required for separating elements can be small. In other words, the transistor and the capacitor are separated by the side of the depth direction and the side of the horizontal direction of the SiO2 layer 3 which is selectively formed and to be a field oxide film. Moreover, as the separation between capacitors is achieved by a P-N junction including a P type region 2, the element separating structure of this DRAM is very simple.

Method of improving silicon-on-insulator uniformity

Abstract: A method of improving silicon-on-insulator uniformity using polishing. A polishing stop layer of substantially uniform thickness is provided having a first side which is made coplanar with a first side of a thicker layer of semiconductor material. A polishing process is applied to a second side of the semiconductor material until a second side of the polishing stop layer is encountered, such that the substantially uniform thickness of the polishing stop layer can be used to define the semiconductor material to a layer of uniform thickness.

Silicon‐on‐insulator material formed by oxygen implantation and high‐temperature annealing: Carrier transport, oxygen activity, and interface properties

Abstract: The crucial roles of high‐temperature annealing (1300–1340 °C) and ambient gas are emphasized by the electrical properties of structure fabricated on silicon‐on‐insulator by deep oxygen implantation. Hall‐effect measurements down to 77 K, as well as the characteristics of front channel and back channel transistors, show that the silicon overlay is quasihomogeneous, as a consequence of drastic improvement of the buried interface region. This is illustrated by the high carrier mobilities (1250 cm2 V−1 s−1 for electrons at 300 K), the dominance of acoustic phonon scattering, and the interface parameters that are more favorable than after low‐temperature anneals and similar to those of bulk Si. The properties and the temperature behavior of oxygen‐related donors are also investigated via the Hall effect. About 1015 cm−3 thermal donors are generated around 450–550 °C, while 1017 cm−3 new donors are formed at 750 °C. New donors presumably originate from the interface states of SiOx precipitates.

A lateral silicon-on-insulator bipolar transistor with a self-aligned base contact

Abstract: A novel lateral bipolar transistor structure in silicon-on-insulator (SOI) is presented. The structure allows for a minimum geometry base width yet still provides for a metal contact to the entire base region. Fabricated transistors exhibit a base resistance of less than 20 Ω.

Method for adhesion of silicon or silicon dioxide plate

Abstract: According to the present invention, a silicon wafer, silicon dioxide wafer or silicon wafer having a silicon dioxide film thereon can be mutually adhered. The procedure for the adhesion is that a refractory metal, such as zirconium, is deposited by sputtering on a flat surface to be adhered, and tightly stacked onto another substrate made of silicon, silicon dioxide or silicon having a silicon dioxide film thereto, and the stacked wafers are heated in an atmosphere of argon containing 4% hydrogen at approximately 650° C. for approximately 2 hours. The heat causes the deposited zirconium to react with the silicon of both the contacting wafers and is converted into a zirconium silicide alloy, which bonds the wafers. If the wafer is silicon dioxide or coated with silicon dioxide, the zirconium reduces the dioxide to produce silicon, which is then alloyed with the zirconium. Refractory metals other than group IVa and group Va elements can adhere silicon to silicon only. Advantages of this adhesion method are: the process is carried out at approximately 650° C., which does not harm fabricated devices; the adhesion withstands temperatures of 1000° C. which are used for fabricating devices; and the processing does not require strict control of the surface conditions. This method can be applied to the process of making SOI, a wafer-scale integrated LSi, or a three-dimensional LSI.

Synthesis of Buried Silicon Compounds Using Ion Implantation

Abstract: Ion implantation is widely used for doping semiconductors at low concentration, but, with the advent of a new generation of high current implanters, synthesizing new materials rather that simply doping them has become feasible. This technique has been successfully applied to fabricating silicon-on-insulator (SOI) structures with oxygen and nitrogen for several years. Since we are interested in understanding the mechanisms of formation of these layers, we have concentrated on sub-stoichiometric implantation doses of oxygen where it is easier to observe the coalescing layer. In order to determine whether this process of compound formation is more general, our studies were expanded to include implantation of the transition metals. Here, elevated substrate temperatures are necessary to minimize Si surface damage. The resulting disilicide layers are of remarkably high quality: they are single crystals in registry with the silicon wafer and they have better residual resistivities than comparable UHV-reacted suicides.

Porous silicon techniques for SOI structures

Abstract: The two principal silicon-on-insulator fabrication techniques are examined. The first is by buried porous Si formation; areas surrounding device islands are converted into porous Si by proper tailoring of the wafer dopant profile. It is known as FIPOS (full insulation by porous oxidized silicon). The second is by epitaxy on porous Si; a uniform surface porous Si layer is used as a seeding layer for low-temperature epitaxy of the device Si. Oxidation of the underlying porous Si layer, via trenches in the device Si, has been improved to the point that defect generation and wafer warpage are avoided. Fabrication of advanced devices on the FIPOS material has shown that the porous silicon technology is among the front-runners for high-performance CMOS LSIs.

Dielectric isolation process using double wafer bonding

Abstract: A method of forming a high quality dielectrically isolated silicon on insulator semiconductor device using a double wafer bonding process. As a result of the double wafer bonding process, the invention significantly reduces the device limitations presently known with dielectric isolation and silicon on insulator structures. The present invention specifically eliminates the need for grinding or polishing the final surface which the devices will be implemented in, thereby eliminating the adverse effects which these mechanical processes impute onto these surfaces. Additionally, the present invention eliminates the need for a thick polycrystalline deposition for the production of the dielectric isolation, thereby eliminating the adverse effects of single crystal bulk defects and the loss of tolerance control due to warpage which would otherwise occur in a dielectric isolated process. Also as a result of the double bonding process, tighter tolerances and more precisely positioned final islands are achieved, thereby allowing for more densely packed or smaller circuits for a given application.

Uniformly Thick Selective Epitaxial Silicon

Abstract: The growth rate of selective epitaxial silicon is a function of the nucleation site seed area and the ratio of the area of the SiO/sub 2/ mask to silicon area exposed. Therefore, with commonly employed IC circuit patterns, it is difficult to achieve, using conventional epitaxial growth conditions, silicon deposit thickness uniformity needed for IC processing. This constitutes one of the main obstacles to utilizing CVD selective epitaxy as an SOI process or as a replacement of LOCOS for oxide isolation. Reported in this publication is a method of growing uniformly thick selective epitaxial silicon on a silicon wafer with SiO/sub 2/ mask openings to the substrate of various dimensions, and with various Si/SiO/sub 2/ area ratios. The desired control of the deposit thickness is achieved at reduced pressures (below 50 torr) and relatively low deposition temperatures (850 +- 10C).

A high current, high voltage oxygen ion implanter

Abstract: A buried oxide dielectric layer, produced in silicon by ion implantation of oxygen has become recognized as a preferred form of SOI (silicon on insulator). In order to form a silicon dioxide layer a stoichiometric amount of oxygen must be introduced into the silicon substrate. Thus very high implant doses, in the range of 1–3 × 10 18 ions/cm 2 are required. The Eaton NV-200 very high current ion implanter has been built to accomplish such high dose implants in commercially reasonable times and bring SIMOX (Separation by IMplanted OXygen) out of the laboratory. In order to maximize beam utilization the conventional practice of scanning the beam over the wafers has been abandoned. A line beam with very uniform current distribution is used and the wafers, mounted on the inside of a spinning drum pass through it. A multi-aperture ion source is used and the circular beam pattern produced from it is shaped into a line at the wafer by beam line ion optical elements. The design and construction of this 200 mA, 200 keV oxygen ion implanter is described. Results of operation at beam currents up to 110 mA are discussed.

Silicon-on-insulator integrated circuits and method

Abstract: Preferred embodiments include silicon-on-insulator structures (30) and integrated circuits include a thin single crystal silicon layer (32) on a silicon dioxide layer (34) which is on a polysilicon layer (36) bonded to a surface-oxidized silicon substrate (42) by a glass layer (38). Also, single crystal silicon layers on oxide on polysilicon substrates and methods of fabrication are included in the preferred embodiments.

Total Dose Hardening of Buried Insulator in Implanted Silicon-on-Insulator Structures

Abstract: Total dose characteristics of the buried insulator in implanted silicon-on-insulator (SOI) substrates have been studied using MOS transistors. The threshold voltage shift of the parasitic back channel transistor, which is controlled by charge trapping in the buried insulator, is reduced by lowering the oxygen dose as well as by an additional nitrogen implant, without degrading the front channel transistor characteristics. The improvements in the radiation characteristics of the buried insulator are attributed to the decrease in the buried oxide thickness or to the presence of the interfacial oxynitride layer formed by the oxygen and nitrogen implants.

Experimental and theoretical study of ultrafast optical switching using guided mode excitation in silicon on sapphire

Abstract: A silicon film sandwiched between a sapphire substrate and a silver layer is used as nonlinear optical waveguide. Light is coupled in the guide by a grating coupler which has been optimized. This device presents fast switchings under a nonlinear regime. A theoretical analysis taking into account both electronic and thermal refractive index variations in silicon well describes the experimental results.

Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation

Abstract: A process for growing silicon on insulator in which complete isolation of the grown silicon of the substrate silicon by an intermediate oxide layer is obtained. A first epitaxial lateral overgrowth technique is used to grow a continuous layer of silicon through seed holes in a patterned oxide layer overlying the silicon substrate. Then the silicon layer is etched to expose the seed holes which are then oxidized to make the oxide layer aperture-free. This is followed by a second epitaxial lateral overgrowth step to replace the silicon etched in the silicon layer to make the layer substantially planar.

Microstructural characterization of nitrogen-implanted silicon-on-insulator

Abstract: The effects of implant dose and postimplant annealing treatment on the microstructure of nitrogen‐implanted silicon‐on‐insulator were studied by cross‐sectional transmission electron microscopy techniques. In the lower dose case (0.75×1018/cm2) an amorphous silicon layer forms after implantation. Annealing at 1200 °C or higher results in a buried polycrystalline α‐Si3N4 layer containing many randomly oriented silicon particles. Higher dose implantation results in an amorphous silicon‐nitride layer. A porous layer also forms in the middle of the amorphous layer if the implant dose is 1.2×1018/cm2 or higher. The crystallization of the amorphous layer in the higher dose cases is shown to happen in two steps. In the first step nucleation and growth of α‐Si3N4 grains occur in the amorphous nitride region to form a spherulitic polycrystalline structure. The second step is the cellular growth of the spherulitic nitride grains into the crystalline silicon regions. Silicon particles are trapped at the cell walls a...

Formation and nondestructive characterization of ion implanted silicon‐on‐insulator layers

Abstract: High‐temperature oxygen ion implantation has been used to form buried oxide layers in silicon single crystals. The ion implantation and substrate variables, particularly the substrate temperature, were optimized to obtain silicon layers with controlled microstructures near the surface. The as‐implanted specimens were subsequently annealed at high temperatures to form a buried SiO2 layer with sharp interfaces and to minimize dislocation densities in the top silicon layers. The specimens were characterized by cross‐section transmission electron microscopy and these results were compared with those obtained using spectroscopic ellipsometry. We discuss the application of the nondestructive scanning ellipsometry technique in the characterization of silicon‐on‐insulator materials.

Anodizable strain layer for SOI semiconductor structures

Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Properties of ion beam synthesized buried silicon nitride layers with rectangular nitrogen profiles

Abstract: SOI (silicon on insulator)-structures were produced by implantation of 330 keV, 14N+-ions with doses ranging from 0.9 to 1.5 × 1018 cm−2 at a target temperature of 500°C into monocrystalline silicon to form buried silicon nitride layers. Post-implantation annealing was done at 1200°C up to 5 h. In this manner silicon nitride compounds with different stoichiometry and structure are produced. After implantation amorphous layers with Gaussian nitrogen profiles up to overstoichiometric concentrations are formed. Annealing leads to the transformation of the Gaussian profiles into rectangular ones if the maximum concentration of the as-implanted distribution does not exceed the value necessary for Si3N4 stoichiometry. In all cases the interfaces between the buried layer and the neighbouring silicon are steep and the structure of the silicon nitride is crystalline. For stoichiometric and overstoichiometric layers a high resistivity in the range of 1014 to 1016 Ω cm was found. After annealing monocrystalline silicon top layers of high quality are formed. A test is reported on the reamorphization of crystalline Si3N4. The results are promising.

A method for effecting adhesion of silicon or silicon dioxide plates.

Abstract: In a procedure for effecting mutual adhesion of a silicon wafer, a silicon dioxide wafer or a silicon wafer (11, 12) having a silicon dioxide film (13, 14) thereon, a refractory metal, such as zirconium, is deposited by sputtering on a flat surface to be adhered, and tightly stacked on to another substrate (15) made of silicon, silicon dioxide or silicon having a silicon dioxide film thereon, and the stacked wafers are heated in an atmosphere of argon containing 4% hydrogen at approximately 650 DEG C for 2 hours. By the heat, the deposited zirconium reacts with the silicon of both the contacting wafers and is converted into zirconium silicide alloy (18) which bonds the wafers. If the wafer is silicon dioxide or coated with silicon dioxide, the zirconium reduces the dioxide to produce silicon, which is then alloyed with the zirconium. Refractory metals other than zirconium, titanium and hafnium can adhere silicon to silicon only. Advantages of this adhesion method are: the process is carried out at approximately 650 DEG C which does not harm fabricated devices, but the adhesion withstands 1000 DEG C which is used for fabricating devices, and the processing does not require strict control of the surface condition. This method is applied for making SOI, a wafer-scale integrated LSI, and three-dimensional LSI.

High performance SOIMOSFET using ultra-thin SOI film

Abstract: Advantages of using an ultra-thin SOI substrate for SOIMOSFET are discussed using a 2- carrier/2-dimensional simulation. Ultra-thin SOIMOSFET has been shown to possess sharp subthreshold slope and high punchthrough resistance nearly independent of doping concentration. Low field mobility in ultra-thin SOIMOSFET has been predicted to increase up to approximately the maximum value which is obtainable in the inversion layer. The disappearance of kink associated with thinning the SOI film has been reproduced in the simulation. Moreover, it has been found that the current overshoot is virtually suppressed in thin-SOI MOSFET, enabling one to obtain a stable current irrespective of pulse intervals. These results bring SOIMOSFETs an anticipation as a promising alternative for bulk MOSFETs in the application of high speed and small-featured devices.

Control gate lateral silicon-on-insulator bipolar transistor

Abstract: The present invention relates to silicon-on-insulator (SOI) gated lateral bipolar transistors that are CMOS compatible. A method is described wherein a heavily doped region is implanted into the base after gate formation to provide a low resistance path to the base contact. A lightly doped region is also provided underneath the gate to minimize base-collector capacitance.