Showing papers on "Silicon on insulator published in 1988"

Bonding of silicon wafers for silicon‐on‐insulator

Abstract: Several aspects of a new silicon‐on‐insulator technique utilizing bonding of oxidized silicon wafers were investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces contacted face‐to‐face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60–85 erg/cm2 at room temperature to ≂2200 erg/cm2 at 1400 °C. The strength was essentially independent of the bond time. Bonds created during 10‐s annealing at 800 °C were mechanically strong enough to withstand the mechanical and/or chemical thinning of the top wafer to the desired thickness and subsequent device processing. A model was proposed to explain three distinct phases of bonding in the temperature domain. Electrical properties of the bond were tested using metal‐oxide‐semiconductor (MOS) capacitors. The results were consistent with a negative charge de...

Fully integrated single-crystal silicon-on-insulator process, sensors and circuits

Abstract: Integrated semiconductor-on-insulator (SOI) sensors and circuits which are electrostatically bonded to a support substrate, such as glass or an oxidized silicon wafer, are disclosed. The SOI sensors and SOI circuits are both formed using a novel fabrication process which allows multiple preformed and pretested integrated circuits on a silicon wafer to be electrostatically bonded to the support substrate without exposing the sensitive active regions of the electronic devices therein to a damaging electric field. The process includes forming a composite bonding structure on top of the integrated circuits prior to the bonding step. This composite structure includes a conductive layer dielectrically isolated from the circuit devices and electrically connected to the silicon wafer, which is spaced form but laterally overlaps at least the active semiconductive regions of the circuit devices. The SOI sensors each include a transducer and at least one active electronic device, which are both made at least in part from a common layer of lightly-doped single-crystal semiconductor material grown on the silicon wafer. After the bonding step, the bulk of the single-crystal wafer is removed, leaving the epitaxial layer containing the circuits and transducers. The epitaxial layer is then patterned into isolated mesas to dielectrically isolate the electronic devices. This patterning step also exposes bond pads, allowing external connections to be readily made to the sensors and circuits. Exemplary solid-state sensors disclosed herein include a capacitive accelerometer and pressure sensor.

A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD

Abstract: A charge-based large-signal transient model for the enhancement-mode thin-film SOI MOSFET in strong inversion, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the predominant short-channel effects in MOSFET's (namely threshold-voltage reduction, drain-induced conductivity enhancement, velocity saturation with mobility degradation, and channel-length modulation) as influenced by the unique features of thin SOI devices (i.e. the presence of an additional back gate and the possibility of a floating film body). It includes a description of generation current due to (weak) impact ionization, which can have a far greater influence on SOI (as compared to bulk) MOSFET's due to the associated charging of the floating body. Measurements on devices of varied geometry show good agreement with model predictions. The model is implemented in SPICE2, to be used for circuit and device CAD, and TECAP, for automated parameter extraction. >

Method and product for fabricating a resonant-bridge microaccelerometer

Abstract: A resonant bridge microaccelerometer is formed using patterned Silicon-on-Insulator (SOI) material. A buried layer is formed in the silicon substrate using preferably oxygen ion implanting techniques. A predetermined proof mass is subsequently formed by selective deposition of an appropriate material on an epitaxially grown layer of silicon generally over the buried layer. The buried layer is subsequently removed by a hydrofluoric acid etch, thereby forming a gap generally everywhere therebetween the proof mass and the supporting silicon substrate, and delineating the resonant microbridges within the microaccelerometer.

Method of making high speed semiconductor device having a silicon-on-insulator structure

Abstract: A CMOS silicon-on-insulation structure is fabricated by first forming an insulating SiO 2 layer on a silicon substrate having a (110) plane. Openings are then formed in the SiO 2 layer to expose a part of the substrate, and a polycrystalline or an amorphous silicon layer is deposited on the SiO 2 layer and in the openings. The deposited silicon layer is divided into islands so that a first island includes one of the openings and a second island does not include any openings. A laser beam is then irradiated onto the islands so as to melt the islands, and when the laser light irradiation is discontinued, the melted islands recrystallize so that the first island forms a (110) plane and the second island forms a (100) plane. A p-channel MOSFET is fabricated on the first island, and an n-channel MOSFET is fabricated on the second island. The thus paired CMOS operates at high speeds, because the p-channel MOSFET using positive holes as the carrier is fast in a (110) crystal, and the n-channel MOSFET using electrons as the carrier is fast in a (100) crystal.

A dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof

Abstract: A DRAM cell structure and a manufacturing method thereof are disclosed, in which a transistor and a capacitor are formed three-dimensionally in an SOI structure The substrate having the SOI structure is fabricated by bonding two silicon substrates sandwiching a silicon oxide layer therebetween A plurality of pillars of silicon layers arranged in a matrix array is formed in the SOI structure by forming a trench in the silicon layers of the SOI The lower portion of the pillar is used as a storage electrode of the capacitor and the upper portion, as active regions of the vertical transistor In the trench, doped polysilicon is filled in a lower portion and functions as a cell plate of the capacitor, thereby a dielectric film being formed on the pillar surface A gate insulating film and a gate electrode thereon are formed on the upper side surface of the pillar The gate electrode is formed self-aligned, connected in the Y-direction but separated in the X-direction, and functions as a word line A connecting line of the upper active region of the transistor functions as a bit line Only two mask processes are needed in fabricating the above DRAM cell, and an isolation between adjacent cells is excellent in spite of a small cell area

Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFETs

Abstract: A proposed breakdown model includes the effects of floating substrate and finite silicon thickness. The calculated I-V characteristics in the breakdown region agree well with the experimental results. The results show that (1) the drain-source breakdown voltage of silicon-on-insulator (SOI) n-MOSFETs increases with increasing channel length, increasing positive substrate voltage, and decreasing silicon film thickness; and (2) SOI n-MOSFETs have higher breakdown voltage than their bulk-silicon counterparts at large gate bias, but lower breakdown voltage at small gate bias. >

Optical waveguides in oxygen-implanted buried-oxide silicon-on-insulator structures

Abstract: An analysis is made of the waveguiding properties of the oxygen-implanted, buried-oxide, silicon-on-insulator structures currently being developed for use in microelectronics. It is found that in spite of the fact that the buried-oxide layer is only a few tenths of a micrometer thick, the single-crystal overlayer can support TEo guided-wave propagation, at subbandgap wavelengths, with losses due to substrate radiation leakage at or below the benchmark level of 1 dB/cm.

Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors

Abstract: Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4*10/sup 16/ cm/sup -3/, the drain saturation current in ultrathin SOI transistors is predicted to be approximately 40% larger than that of bulk structures. An increase of approximately 30% is seen in measurements made on devices in 1000-A SOI films. >

High-temperature silicon-on-insulator electronics for space nuclear power systems: requirements and feasibility

Abstract: The authors performed a study to determine whether silicon very large-scale integrated circuits (VLSICs) can survive the high temperature (up to 300 degrees C) and total-dose radiation environments (up to 10 Mrad over a 7-10-y system life) projected for a very-high power space nuclear reactor platform. It is shown that circuits built on bulk epitaxial silicon cannot meet the temperature requirement because of excessive junction leakage currents. However, circuits built on silicon-on-insulator (SOI) material can meet both the radiation and temperature requirements. It is also found that the temperature dependence of the threshold voltage of the SOI transistors is less than that of bulk transistors. Survivability of high-temperature SOI VLSICs in space, including immunity to transient and single-event upset, is also addressed. >

Lattice mismatched hetrostructure optical waveguide

Abstract: The invention comprises processes and heterostructure products defining silicon on insulator waveguides (80, 88, 90, 106, 112, 120, 122) that are suitable for use with light in the 1.3, 1.6 μm or greater wavelengths. Silicon is deposited on an insulator layer 12 on a crystalline substrate 10 and grown or regrown in crystalline form. The silicon is then etched or formed into a waveguide structures.

From substrate to VLSI: investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomena

Abstract: A silicon-on-insulator (SOI) technology with a hardened variant is presented, focusing on some of the weak points that could impede the progress of SOI toward the production of high-speed hardened VLSI. The devices described here use the LOCOS isolation method instead of the commonly used MESA and a thin active silicon layer on which no epitaxy takes place. Dose and dose rate tests were performed on both technologies and on various circuits and special-purpose devices. An analysis of the sensitivity of the circuits to single-event upset, (SEU) was made, and a hardness limitation coming from an ion-induced transient caused by substrate-related phenomena was found. Dose, dose rate, and SEU behavior are related to the structural characteristics mentioned above. >

Formation of submicron silicon‐on‐insulator structures by lateral oxidation of substrate‐silicon islands

Abstract: Fully isolated islands have been formed in silicon using selective, lateral thermal oxidation at the base of 250‐nm‐wide structures. The final structure consists of substrate silicon on thermal oxide on substrate silicon. The process begins with the definition of 250‐nm‐wide islands that are capped on the top and sidewall with a silicon dioxide/silicon nitride oxidation mask. The structure is then isotropically or anisotropically recess etched and thermally oxidized to produce isolated silicon islands. Our experiments show that the quality of the silicon‐on‐insulator structure depends on the oxidation mask, the island dimension, the profile of the recess etch, and the oxidation time and temperature. The degree of isolation can be tailored by controlling the lateral oxidation of the filament connecting the island to the underlying substrate. By this technique we have formed silicon filaments of 10 to 100 nm in width.

Silicon-on-insulator and buried metals in semiconductors

Abstract: The symposium presented in this book reported on key developments for overcoming limiting problems with various SOI and SOS technologies. Several technologies now are sufficiently well understood to be able to provide large area, low defect density films. A broad base of work identifying fundamental mechanisms in the SIMOX process has led to the ability to produce very dislocation density films by a multiple step process or by ordered precipitates. Zone melting, recrystallization with low defect densities, of large wafers, and of multilayer structures were also described. High quality ultra-thin SOS film results were presented, and the wafer bonding technique has been shown capable of producing uniform films of only 500 A thickness.

Raman scattering measurement of silicon‐on‐insulator substrates formed by high‐dose oxygen‐ion implantation

Abstract: Raman scattering spectroscopy is applied to an evaluation of silicon‐on‐insulator substrates formed by high‐dose oxygen‐ion implantation. This implantation creates a superficial crystal silicon/buried oxide/substrate silicon structure. Two peaks are found in the Raman spectra of the substrates. Their intensity ratio varies with the exciting laser wavelength. One narrow peak at 521 cm−1 is assigned to optical phonons in the substrate silicon, and the other broader peak at lower frequency is assigned to the superficial silicon. With an increase in postimplantation annealing temperature, the Raman peak frequency of the superficial silicon increases and the linewidth becomes narrower, approaching the values of single‐crystal silicon. One possible interpretation for the Raman peak downshift is that the oxygen‐ion implantation causes structural deformations of the superficial silicon layer, mainly oxygen precipitation and defect generation.

Silicon and silicon dioxide thermal bonding for silicon‐on‐insulator applications

Abstract: There has been a good deal of interest recently in the applicability of thermal bonding to silicon‐on‐insultator (SOI) technology. Thermal bonding (also called direct bonding) is accomplished by mating polished, properly hydrolyzed silicon and/or silicon dioxide surfaces, which are then annealed to promote diffusion bonding. In order to produce high‐quality SOI layers it must be demonstrated that the interface betweeen the wafers is void‐free over the entire surface of the wafer (4‐in. wafers in our study). We have found that the standard annealing step which has been used by other groups to form the wafer bond must be followed by a hyperbaric, high‐temperature annealing cycle in order to produce interfaces which are completely void‐free. In addition, we have found that mating the wafers in a controlled atmosphere is necessary to insure that voids do not remain after the thermal processing is complete. We shall present transmission electron micrographs which reveal the morphology of the bonded interface on an atomic scale. We shall submit C‐scan acoustic micrographs and infrared transmission thermographs which display the areal nature of the bonding voids.

Silicon-on-insulator and buried metals in semiconductors : symposium held November 30-December 3, 1987, Boston, Massachusetts, U.S.A.

Abstract: The symposium presented in this book reported on key developments for overcoming limiting problems with various SOI and SOS technologies. Several technologies now are sufficiently well understood to be able to provide large area, low defect density films. A broad base of work identifying fundamental mechanisms in the SIMOX process has led to the ability to produce very dislocation density films by a multiple step process or by ordered precipitates. Zone melting, recrystallization with low defect densities, of large wafers, and of multilayer structures were also described. High quality ultra-thin SOS film results were presented, and the wafer bonding technique has been shown capable of producing uniform films of only 500 A thickness.

Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure

Abstract: A process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure. After the processing of polysilicon layers (14, 18), dielectric layers (12, 16, 20, 26), an epitaxial region (24) and a nitride layer (28), a second substrate (30) is bonded to the nitride layer (28) and the first substrate (10) is removed. This allows for an epitaxial region (24) which is isolated from the substrate (30).

Total-dose hardness assurance issues for SOI MOSFETs

Abstract: The top-gate, back-gate, and sidewall responses of SIMOX and ZMR SOI/MOS transistors to 10-keV X-ray and Co-60 irradiation are compared. For top-gate and sidewall insulators, Co-60 and 10-keV X-ray irradiations at matched dose rates lead to nearly identical responses. Back-gate response, on the other hand, depends strongly on radiation energy and buried insulator thickness. Different X-ray to Co-60 correlation factors can be observed for other technologies with different sidewall and buried insulator materials and thicknesses. It is demonstrated that it is not possible to define a generic set of worst-case radiation bias conditions for all SOI technologies, as back-gate radiation response can be a strong function of transistor drain bias during exposure. However, the magnitude of this effect can vary with material and device processing, and the detailed changes in Si island potential and insulator electric fields that cause this behavior are not yet understood. Postirradiation effects are also addressed briefly. >

Heterojunction bipolar transistor with SiGe

Abstract: A heterojunction bipolar transistor has an emitter which comprises an expitaxial layer of silicon grown on a silicon and germanium base layer. The active region of the transistor comprises a semiconductor having a silicon/silicon and germanium strained lattice and the silicon and germanium base layer is grown on a silicon substrate while maintaining commensurate growth. The lattice strain is such as to produce a predetermined valence band offset at the emitter/base junction. The mobility in the base is also enhanced over that of an unstrained alloy of the same composition.

Silicon on insulator semiconductor composition containing thin synthetic diamone films

Abstract: A process is provided for making a semiconductor element comprising a single-crystal layer of silicon on a diamond insulator.

LCMOS displays fabricated with implant treated silicon wafers

Abstract: An improved LCMOS display device employing a silicon-on-insulator (SOI) substrate (41) having an epitaxial silicon layer (15) lying over an implant-generated dielectric layer (13). MOS device and capacitor elements (17, 19, 21) used to activate the display are formed and interconnected in the epitaxial silicon (15). The implant-generated dielectric layer (13) and underlying silicon substrate (41) also serve as capacitor elements, thereby simplifying the structure and fabrication of the display device and providing improved operation through improved isolation of the MOS device elements formed in the epitaxial silicon (15) from the substrate (41).

Static and dynamic transconductance model for depletion-mode transistors: a new characterization method for silicon-on-insulator materials

Abstract: The dynamic transconductance method is generalized for depletion-mode transistors (DMTs) and used to characterize the interface trapping properties and film doping on silicon-on-insulator (SOI) structures. This method is based on an analytical model of the transconductance for static, dynamic, and high-frequency operation in the linear region. >

A new analytical model for the two-terminal MOS capacitor on SOI substrate

Abstract: An analytical model for the two-terminal metal-oxide-semiconductor-oxide-semiconductor (MOSOS) structure, which takes into account the width of the accumulation layer in the SOI film and the space-charge region in the underlying Si substrate, is presented. The results of the model are compared with results one-dimensional (1-D) numerical simulations for a uniformly doped Si film and substrate, showing considerable improvement in accuracy compared to traditional models. >

Method for forming epitaxial silicon on insulator structures using oxidized porous silicon

Abstract: A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate. Planarization of the structure and exposure of the epitaxial surfaces provides electrically isolated islands of monocrystalline silicon for bipolar and field effect device fabrication. A CMOS implementation of the epitaxial islands is readily undertaken by selective counterdoping in the presence of a mask.

Deep states in silicon‐on‐insulator substrates prepared by oxygen implantation using current deep level transient spectroscopy

Abstract: Current deep level transient spectroscopy was applied using enhancement n‐channel metal‐oxide‐semiconductor field‐effect transistors fabricated in silicon‐on‐insulator substrates (prepared by oxygen implantation) to study the deep levels existing in the substrates. The current transients are not affected by the large series resistances which affect the measurement of capacitance transients on thin films. For the transistors used in this work a hole trap was found with energy ET=0.63 eV above the valence‐band edge. The concentration and capture cross section of this state were estimated to be 1014 cm−3 and 10−16 cm2, respectively.

The use of multiple oxygen implants for fabrication of bipolar silicon-on-insulator integrated circuits

Abstract: A description is given of the radiation improvements obtained by fabricating bipolar integrated circuits on oxygen-implanted silicon-on-insulator substrates that were manufactured with multiple (low-dose) implants. Bipolar 74ALS00 gates fabricated on these substrates showed an improvement in total dose and dose-rate radiation response over identical circuits fabricated in bulk silicon. Defects in SIMOX material were reduced by over four orders of magnitude. The results demonstrate that bipolar devices, fabricated on multiple-implant SIMOX substrates, can compete with conventional dielectric isolation for many radiation-hardened system applications. >

Demonstration of the benefits of SOI for high temperature operation

Abstract: Summary form only given. To evaluate the performance of SOI circuits at high temperatures, CMOS 4K SRAMs were fabricated on SIMOX (separation by implantation of oxygen) and bulk starting material. Four varieties were included in this study: bulk (5 mu m epi on n/sup +/), and SIMOX/SOI with three silicon-layer thicknesses (0.5 mu m, 0.75 mu m, and 1.0 mu m). This combination allows the assessment of three device structures: standard bulk devices, standard SOI devices (S/D contacting the buried oxide), and semi-bulk SOI devices which operate like bulk devices but are dielectrically isolated. All the SOI SRAMs were functional to the maximum temperature available, 300 degrees C. The bulk circuits also functioned at elevated temperatures, but lost functionality between 250 degrees C and 275 degrees C due to the rapidly increasing leakage current associated with the well junction. The synchronous access time increased approximately linearly with temperature for all devices, and was nearly twice the measured room-temperature value at 300 degrees C. Leakage current increased strongly with temperature for all devices, with the thin SOI devices having the least static current at the highest temperatures. >