Showing papers on "Silicon on insulator published in 1990"

Silicon-on-insulator 'gate-all-around device'

Abstract: Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >

Method of producing a thin silicon-on-insulator layer

Abstract: 2066193 9105366 PCTABS00004 A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy (24) includes properly doping a prime silicon wafer (20) for the desired application, growing a strained Si1-x Gex alloy layer (24) onto seed wafer (20) to serve as an etch stop, growing a silicon layer (26) on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer (20) and a test wafer (30), bonding the oxide surfaces of the test (30) and prime wafers (20), machining the backside of the prime wafer (20) and selectively etching the same to remove the silicon (20 and 22) removing the strained alloy layer (24) by a non-selective etch, thereby leaving the device region silicon layer (26). In an alternate embodiment, the process includes implanting germanium, tin, or lead ions to form the strained etch stop layer (24).

SOI diaphragm sensor

Abstract: The present invention relates to the fabrication of diaphragm pressure sensors utilizing silicon-on-insulator technology where recrystallized silicon forms a diaphragm which incorporates electronic devices used in monitoring pressure. The diaphragm is alternatively comprised of a silicon nitride having the necessary mechanical properties with a recrystallized silicon layer positioned thereon to provide sensor electronics.

Silicon fusion bonding for fabrication of sensors, actuators and microstructures

Abstract: Silicon fusion bonding (SFB) is the joining together of two silicon wafers without the use of intermediate adhesives. The technology has been used to fabricate silicon-on-insulator (SOI) substrates and silicon power devices, and also has wide applications in the fabrication of silicon sensors, actuators and other microstructures. This paper reviews the development and current status of SFB. A history of the technology from the early 1960s to the present is presented. Process techniques necessary to incorporate SFB successfully into silicon micromachining processes are discussed, and examples of successful SFB structures are presented. Comparisons to competing techniques are made, and the potential for future development of SFB structures is discussed. Silicon fusion bonding presents major new possibilities in the design of silicon micromachined structures when combined with other available processing techniques. SFB has already been used in novel accelerometers, high-temperature pressure sensors, ultraminiature pressure sensors and high over-range pressure sensors. SFB does not appear to be the technique of choice for VLSI SOI technology, but it is highly viable for use in silicon microstructures, and it is incumbent on the micromachining community to pursue further development of the technology. With the development of ‘smart’ power devices occurring in parallel with the development of ‘smart’ sensors, it is to be hoped that evolution of SFB for both microstructures and power devices will continue and will provide cross-fertilization between the two fields.

Temperature dependence of threshold voltage in thin-film SOI MOSFETs

Abstract: A first-order model for the temperature dependence of threshold voltage in thin-film silicon-on-insulator (SOI) n-MOSFETs is described. The temperature dependence of the threshold voltage of thin-film SOI n-channel MOSFETs is analyzed. Threshold voltage variation with temperature is significantly smaller in thin-film (fully depleted) devices than in thick-film SOI and bulk devices. The threshold voltage is shown to be dependent on the depletion level of the device, i.e. whether it is fully depleted or not. There exists a critical temperature below which the device is fully depleted, and above which the device operates in the thick-film regime. >

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET

Abstract: A fully depleted lean-channel transistor (DELTA) that has a gate with a vertical ultrathin SOI structure is reported. In the deep submicrometer region, selective oxidation is useful in realizing SOI isolation. It provides high crystalline quality, as good as that of conventional bulk single-crystal devices. Using experiments and three-dimensional simulation, it was shown that the gate structure has effective channel controllability and its vertical ultrathin SOI structure provides superior device characteristics. >

Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs

Abstract: A model developed to explain conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs is discussed. It is found that, unlike that which occurs in thin-film fully depleted n-channel devices, there is little or no coupling between the front and back gates, unless the surface-state density is so high that the film remains depleted even when an accumulation channel is formed. The apparent front threshold shift is explained by back-gate modulation of a body current, flowing from the source to the drain. Indeed, the body of the device presents a p/sup +/-p/sup -/-p/sup +/ structure whose conductivity is controlled by the depth of the depletion zones arising from the top and the bottom of the silicon film. The model is used to calculate drain current as a function of front- and back-gate bias as well as output characteristics. >

Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs

Abstract: Analytical models are proposed for thin- and ultra-thin film silicon-on-insulator (SOI) MOSFETs operating in weak or strong inversion. The models take into account all the device parameters. The cases of two and three interfaces with a silicon substrate are considered in the modeling and compared with one another. These models give the main electrical MOSFET parameters in ohmic operation (subthreshold swing and threshold voltage) for these structures. The basic approximation is the consideration of a linearly varying potential in the Si film, which has been inferred on the basis of numerical simulations. Various behaviors depending on the Si film and the buried insulator thickness as well as the interface charges, Si film doping, or substrate regime are simulated to assess the properties and the performances of SOI MOS transistors and to validate the analytical models. >

Manufacturing ultra-thin wafer using a handle wafer

Abstract: A process including bonding a first device wafer to a handle wafer by an intermediate bonding oxide layer and thinning the device wafer to not greater than 7 mils. An epitaxial device layer of under 1 mil may be added. Device formation steps are performed on a first surface of the first device wafer. This is followed by removing the handle wafer to produce a resulting wafer having substantially the thickness of the first device layer. To produce a silicon on insulator (SOI), a third device wafer is bonded to the first surface of the first device wafer by the intermediate oxide layer and the third wafer is thinned to not greater than 40 microns. The first and third device wafers form the resulting SOI wafer.

Single-event charge enhancement in SOI devices

Abstract: Studies are presented of single-particle ion effects in body-tied CMOS/silicon-on-insulator (SOI) devices. It is shown that two mechanisms can contribute to SOI soft-error rates: a direct ion-induced photocurrent and a local lateral bipolar current. The total amount of charge collected is sensitive to the relative locations of the ion strike and the body-to-source tie. >

Esd protection for soi circuit

Abstract: PURPOSE: To make a protective circuit decreasing the thermal dissipation requirements of a thin semiconductor layer in SOI structure making feasible of the easy manufacture and the compatibility with another transistor on a chip by a method wherein a semiconductor body specifying a conductive channel between a semiconductor drain and a semiconductor source is provided with a FET formed of an SOI structure CONSTITUTION: An electrostatic discharge(ESD) protective device for SOI circuit is composed of an SOI structure containing a semiconductor material 20 conforming to the formation of a transistor therein, a conductor transmitting the signals relating to this transistor circuit and a field effect transistor 14 connected to this conductor conducting an ESD current and provided with a semiconductor body specifying a conductive channel 26 between a semiconductor drain 24 and source 22 while the semiconductor body contains the FET 14 formed of the SOI structure For example, the bulk material 26 in the conductive channel of the FET 14 is electrically separated from the residual semiconductor material 20 while a contact for connecting to the source region 22 is provided on a gateconductor 30

Electrical transient study of negative resistance in SOI MOS transistors

Abstract: Using electrical transients, we have investigated the negative resistance observed in the output characteristics at high gate voltages in MOS transistors made in SOI films. We show experimentally that this effect is due to a temperature rise in the device itself. This results from the poor thermal conductivity of the buried oxide of the SOI structure.

Silicon Wafer Bonding Mechanism for Silicon-on-Insulator Structures

Abstract: X-ray diffraction topography and tensile testing are used to study the perfection of bonded interfaces in the sandwich structure where one of the two silicon wafers used had an SiO2 layer applied to it first. The tensile strength and the formation of unbonded areas (voids) were compared to the cases where two bare silicon wafers were used and where both wafers were coated with oxide. There are two mechanisms for wafer bonding: one is for a lower temperature and another is for a higher temperature range. It is concluded that a strong affinity between the two wafers at low temperatures is essential to obtaining tight bonding after a high-temperature anneal. A proper amount of H, OH and H2O on the wafers plays an important role in good chemical bonding below 800°C. Above 1000°C an interaction between adjacent atoms to create covalent bonding and deformation of the SiO2 layer are effective in establishing good bonding.

Modes of operation and radiation sensitivity of ultrathin SOI transistors

Abstract: Improved short-channel behavior, reduced subthreshold slopes, and mobility enhancements previously observed in NMOS transistors made in thin, fully depleted silicon-on-insulator (SOI) films are discussed. These results were obtained with the back interface held in depletion during operation. It is shown from basic principles of device operation that the observed performance improvements are sensitive to the applied substrate voltage. In addition, the exposure of the back interface to the surface depletion region in these devices makes the transistor performance sensitive to radiation-induced charging effects at the back interface. The anticipated effects of radiation on threshold voltage, subthreshold slope, and mobility in ultrathin, fully depleted SOI transistors are discussed, and an estimate is made of the expected radiation sensitivity of these parameters for a typical ultrathin SOI technology. >

An analytical model for the MISIS structure in SOI MOS devices

Abstract: A general analytical model is presented for the 1-D MISIS (metal-insulator-semiconductor-insulator-semiconductor) structure which occurs in SOI MOS devices. The model takes into account inversion, depletion and accumulation layer widths in both semiconductor regions, fixed isolator charges as well as interface trap charges. The model is compared with numerical simulations and shows very good agreement. Finally, it is applied for calculating the threshold voltage and the subthreshold slope in SOI n MOS transistors and is proven to be superior to conventional analytical models, especially in the thin film regime.

Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning

Abstract: A method for forming a thin crystal layer of silicon on top of a insulating layer that is supported by a silicon wafer used for electronic device applications. Carbon ions are implanted in a silicon wafer in order to form an etch stop. Said wafer is bonded to a supporting wafer that has an insulating surface layer of silicon oxide or silicon nitride. The silicon substrate of the implanted wafer is removed using an alkaline etching solution or grinding and alkaline etching. The remaining carbon implanted layer forms the thin silicon layer.

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

Abstract: A novel method for obtaining ultra-thin, defect-free silicon on insulator (SOI) film is introduced. This technique uses epitaxial lateral overgrowth of Si (ELO) and chemical-mechanical polishing (CMP). SOI films with thicknesses of 100 nm were obtained. These films were used in fabrication and dual poly CMOS devices. The quality of the SOI film obtained is the same as that of bulk silicon, and the device characteristics are comparable with those of devices fabricated on bulk. A minimum geometry unloaded inverter ring oscillator on SOI film obtained by ELO and CMP showed a speed improvement of 3* over the bulk devices. >

Two-dimensional analytic modeling of very thin SOI MOSFETs

Abstract: An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V/sub DS/. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic. >

Silicon-on-insulator 'gate-all-around' MOS device

Abstract: The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described. >

Semiconductor memory device and manufacturing method thereof

Abstract: Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor formed in the SOI substrate and an Esaki diode is positioned on the MOS transistor. The memory device also comprises a memory cell provided with a plurality of tunnel diodes connected to one of the impurity regions constituting the FET formed in the semiconductor substrate, and another memory cell provided with an Esaki diode formed in an self-alignment by a solid phase diffusion. In manufacturing the semiconductor memory device, the MOS transistor and the Esaki diode, which collectively form a memory cell, are integratedly formed one upon the other. The MOS transistor is formed in a semiconductor substrate using an SOI structure so as to prepare a memory cell which does not include a parasitic pn-junction.

Analysis of the kink effect in MOS transistors

Abstract: An analysis of the kink effect in MOS transistors that provides a comprehensive view of the kink effect in bulk silicon MOSFETs and SOI devices is presented. This analysis enables a quantitative description of the excess drain current to be obtained for room and liquid-helium temperatures. In particular, it is found that the kink effect in a MOS transistor can be simply modeled by a body effect. >

SOI design for competitive CMOS VLSI

Abstract: Device simulations using a physical SOI MOSFET model implemented in SPICE2 predict that properly designed silicon-on-insulator (SOI) has a substantial advantage over bulk CMOS VLSI with regard to hot-carrier-induced degradation. The simulations show that the (short-) n-channel SOI MOSFET, designed with moderately thin (not ultrathin) film having complete depletion in the film and at the back surface, and without an LDD region, will degrade much more slowly than a contemporary bulk MOSFET with an LDD. This suggests that the 5-V source can be retained for submicrometer SOI CMOS, whereas it must be lowered for bulk CMOS. The simulations and the optimal SOI designs they suggest are supported by measurements of thin-film and bulklike MOSFETs fabricated in SIMOX SOI. >

Silicon Wafer-Bonding Process Technology for SOI Structures

Abstract: The perfections of bonded interfaces with the sandwich structure of a SiO2 layer are studied by the x-ray diffraction topogrcphy and the tensile testing. The tensile strengths of this structure were compared with that for two bare silicon wafers and two wafers with oxide coatings. It is discussed that a proper amount of H, OH and HzO on wafers play an important role on the chemical bonding under 800C and an interaction between adjacent atoms and the deformation of SiO2layer-are effective for tight bonding over 1000C.

Numerical and charge sheet models for thin-film SOI MOSFETs

Abstract: Numerical charge sheet models applicable for all bias conditions are presented for the channel currents of long-channel SOI MOSFETs. From a comparison of the two models it is shown that the charge sheet analytic model accurately predicts the channel currents from weak to strong inversion regions. The results include analytic expressions for the drift and diffusion current components of individual channel currents, the front-gate and back-gate interaction parameter, and an analytic correlation between the surface potentials of the front and back channels when there is coupling between the two gates under nonthermal equilibrium conditions. The effect of SOI (silicon on insulator) film thickness on the drain current was investigated under different bias conditions for the back gate, and it was found that thin films are beneficial from the point of increased drain currents if the back channel is in depletion or inversion. It is also shown that, in addition to the charge coupling effects, dynamic interaction between the channels exists if the static current in one of the channels saturates. >

SOI/semiconductor heterostructure fabrication by wafer bonding of polysilicon to titanium

Abstract: This is a method of forming a semiconductor-on-insulator wafer from two individual wafers. The method comprises: forming a layer of metal (e.g. titanium 24) on a first wafer; forming an insulator (e.g. oxide 32) on a second wafer; forming a bonding layer (e.g. poly 38) over the insulator; anisotropically etching the bonding layer forming chambers in the bonding layer; stacking the first and second wafers with the metal against the second wafer's bonding layer; forming a chemical bond between the metal layer and the bonding layer (e.g. between the titanium 20 and the poly 38) in a vacuum chamber, thereby creating micro-vacuum chambers (42) between the wafers; selectively etching the second wafer to form a thin semiconductor layer (e.g. epi layer 30). This is also a semiconductor-on-insulator wafer. The wafer comprises: a substrate (e.g. semiconductor substrate 20); a layer of metal (e.g. titanium 24) and semiconductor (e.g. silicide 40) over the substrate; a bonding layer (e.g. poly 38) over the metal and semiconductor, with micro-vacuum chambers (42) in the bonding layer; an insulator (e.g. oxide 32) over the bonding layer; and a single-crystal semiconductor layer (e.g. epi lyaer 30) over the insulator.

Method for preparing a substrate for forming semiconductor devices

Abstract: A new method of preparing an exceedingly flat substrate for forming semiconductor devices having an SOI structure is disclosed. In this process at least a first wafer made of silicon single crystal is concavely warped beforehand. A second silicon single crystal wafer is bonded to the concavely warped side of the first wafer with an oxide film interposed between the first and the second wafers. Subsequently the wafers are subjected to polishing and/or etching so that the second wafer bonded is thinned into a thin film to prepare a substrate for forming semiconductor devices having a SOI structure. At this time the polishing and/or etching cause the bonded wafers to be warped convexly to offset the concavity of the first wafer, resulting in realization of a precisely flat substrate for forming semiconductor devices having an SOI structure. Further, at the time of determining the magnitude of the warp of the first wafer beforehand, an approximate linear equation is used which shows a relationship between the warps formed before and after the formation of the oxide film.

Method for preparing a substrate for forming semiconductor devices by bonding warped wafers

Abstract: A new method of preparing an exceedingly flat substrate for forming semiconductor devices having an SOI structure is disclosed. In this process at least a first wafer made of silicon single crystal is concavely warped beforehand. A second silicon single crystal wafer is bonded to the concavely warped side of the first wafer with an oxide film interposed between the first and the second wafers. Subsequently the wafers are subjected to polishing and/or etching so that the second wafer bonded is thinned into a thin film to prepare a substrate for forming semiconductor devices having a SOI structure. At this time the polishing and/or etching cause the bonded wafers to be warped convexly to offset the concavity of the first wafer, resulting in realization of a precisely flat substrate for forming semiconductor devices having an SOI structure. Further, at the time of determining the magnitude of the warp of the first wafer beforehand, an approximate linear equation is used which shows a relationship between the warps formed before and after the formation of the oxide film.

Integrated circuit device particularly adapted for high voltage applications

Abstract: A silicon on insulator of integrated circuit comprising a plurality of components typically adopted for high voltage application having a semiconductor substrate of a first conductivity type, an insulating layer provided on the substrate, a semiconductor layer provided on the insulating layer, a number of laterally separated circuit elements forming parts of a number of subcircuits provided in the semiconductor layer, a diffusion layer of a second conductivity type opposite to that of the first conductivity type provided in the substrate and laterally separated from all the other circuit elements and means for holding the diffusion layer at a voltage at least equal to that of the highest potential of any of the subcircuits present in the integrated device.