Showing papers on "Silicon on insulator published in 1995"

Silicon on insulator material technology

Abstract: A silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen. The basic phenomena, and the first physical and electrical characterisations are discussed briefly.

Electrical Characterization of Silicon-on-Insulator Materials and Devices

Abstract: 1. Introduction. 2. Methods of Forming SOI Wafers. 3. SOI Devices. 4. Wafer Screening Techniques. 5. Transport Measurements. 6. SUS Capacitor Based Characterization Techniques. 7. Diode Measurements. 8. Transistor Characteristics. 9. Transistor Based Characterization Techniques. 10. Monitoring the Transistor Degradation. Index.

High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Airbag application: a microsystem including a silicon capacitive accelerometer, CMOS switched capacitor electronics and true self-test capability

Abstract: A low cost, high reliability accelerometer microsystem designed for crash sensing in automotive airbag electronic control units is presented. The proposed microsystem offers high level output, on-line self-test function, small size (3.5 mm × 3.5 mm × 1.15 mm), and high design flexibility thanks to a two-chip construction. The sensitive part is a surface micromachined capacitive interdigitated structure realized from a SIMOX SOI substrate. The accelerometer operates in a closed loop mode using electrostatic feedback with conditioning circuitry realized in a 2 μm CMOS process. A high performance readout circuit using switched capacitors has been developed. Behavioural simulation results show a bandwidth of 630 Hz at ±50 g with 5 V power supply. The fabrication process includes the realization of a free-standing seismic mass by means of reactive ion etching and sacrificial oxide etching, the mechanical protection of the sensing element with a thin silicon cap bonded onto the structured SOI wafer, and eventually the electrical connection with the ASIC by flip-chip bonding. Preliminary results are very encouraging: dynamic actuation of the sensing elements is optically tested, with a yield of 70% at a prototype level. Excellent shock resistance and low internal stress are observed.

"Smart cut": a promising new SOI material technology

Abstract: Silicon On Insulator technologies appear to be a key issue for low-power, low-voltage technologies (/spl ap/1.5 V) and will play a major role in ULSI developments. Today two SOI material technologies are in competition in the very thin SOI film market: SIMOX (Separation by IMplanted OXygen) and BESOI (Bond and Etch Back SOI) Technology. We have developed a new SOI material technology using a bonding technique combined with an ion implantation step, which aims to overcome the remaining limitations of both the above techniques. This process was developed as the "IMPROVE" (IMplanted PROtons Voids Engineering) process and is henceforth referred to as "Smart-cut". The process is implemented for fabrication of Unibond wafers.

Method and structure for providing ESD protection for silicon on insulator integrated circuits

Abstract: A method and structure for providing ESD protection for Silicon-On-Insulator (SOI) integrated circuits. The ESD protection circuit includes an electrically conductive pad and first conductor segment fabricated over an insulating layer. The first conductor segment connects the pad directly to a first node, without an intervening input resistor. A first diode is fabricated over the insulating layer and connected between the first node and a first voltage supply rail. Similarly, a second diode is fabricated over the insulating layer and connected between the first node and a second voltage supply rail. Ballast resistors can be included in series with each of the diodes. A cross power supply clamp, also fabricated over the insulating layer, is connected between the first and second voltage supply rails. The first node of the ESD protection circuit is coupled to the SOI integrated circuit to be protected. The ESD protection circuit can be fabricated on a minimum number of silicon islands to improve local thermal spreading. Improved ESD protection is provided to input, output, and I/O pins of an SOI integrated circuit, while promoting high speed signal transfer between these pins and the integrated circuit.

Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer

Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options. Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented. Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. .linevert split.V tn .linevert split.=.linevert split.V tp .linevert split.).

SOI 'SIMOX'; from bulk to surface micromachining, a new age for silicon sensors and actuators

Abstract: Separation by ion implantation of oxygen (SIMOX), today an industrial 'silicon on insulator (SOI) substrate', allows a number of improvements for silicon sensors or actuators. For piezoresistive detection, the silicon top layer (0.2 μm thick) is used as an active material with the excellent properties of the single-crystalline silicon. Thanks to its very good electrical insulation from the substrate, high temperature sensors (up to 300 °C) with low noise and high dynamic range can be obtained. These devices are generally and preferably made by bulk micromachining for high performance sensors. Another important aspect of this substrate is its ability to get, by epitaxy, a high mechanical quality silicon layer (thickness > 10 μm) for surface micro-machining and the electronic circuits integration for smart sensors. Capacitive detection seems to be most suitable for miniaturised and cheaper surface microstructures. In the case of sensors (pressure or acceleration) with the detection axis perpendicular to the substrate, a higher capacitance variation is obtained due to the thinness of the SiO 2 sacrificial layer (0.4 μm). This high sensitivity allows a reduction of the sensor area. For acceleration sensors with the detection axis parallel to the substrate, the high thickness of the epitaxial silicon layer allows high stiffness ratio which reduces the sticking effect. Moreover, deep dry etching of silicon, which is today a mature technology, provides higher capacitance variation. The last but not the least advantage is the possibility, thanks to the low thickness of the superficial stack (0.6 μm for both layers), to get localised buried electrodes by deep implantation before the epitaxial process. With this extra electrode, the parasitic capacitance can be reduced and the characteristics of the sensor or the actuator improved.

Integrated optical directional couplers in silicon-on-insulator

Abstract: Silicon-on-insulator (SOI) technology offers tremendous potential for integration of optoelectronic functions on a silicon substrate The authors have demonstrated an integrated 3 dB optical directional coupler using SOI rib waveguides The device has an excess insertion loss of 19 dB and represents a key component for the realisation of wavelength filters in silicon integrated circuit technology

Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFETs

Abstract: Partially-depleted (PD) SOI MOSFETs offer improved threshold control and sensitivity over fully depleted devices, but the effects of dynamic floating-body charging on the threshold voltage VT(t) can possibly lead to instabilities in PD/SOI circuits. We show in this paper that the dynamic charging of the body can also induce a parasitic bipolar-transistor (BJT) transient current which can be significant even at low voltages well below the drain-source breakdown defined by the BJT. Our results indicate that if device/circuit design allows substantial variation of the body charge, then the transient BJT current could be large enough to upset the logic or memory (SRAM or DRAM) function of a chip. They further show that such an upset becomes more probable as the device is scaled, and they give insight regarding device and circuit design to reduce the probability.

A physical charge-based model for non-fully depleted SOI MOSFET's and its use in assessing floating-body effects in SOI CMOS circuits

Abstract: A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein. >

Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory

Abstract: An SOI DRAM includes a direct body contact between the SOI layer and the silicon substrate, and field-shield isolation positioned on the surface of the SOI structure which extends over the direct body contact. Deep trench storage capacitors are positioned adjacent the direct body contact.

Silicon on insulator Mach–Zehnder waveguide interferometers operating at 1.3 μm

Abstract: Mach–Zehnder (MZ) waveguide interferometers integrated on SOI (silicon on insulator) for 1.3 μm operation are studied on the basis of the large cross‐section single‐mode rib waveguide condition and the free‐carrier plasma dispersion effect in Si wafer direct bonding SOI by back‐polishing. And the MZ interferometers are fabricated by using KOH anisotropic etching. Their insertion losses and modulation depths are measured to be 4.81 dB and 98%, respectively, at the wavelength of 1.3 μm when a forward bias voltage applied to a p+n junction is 0.95 V and the active zone length of the MZ interferometers is 816.0 μm.

Electron mobility behavior in extremely thin SOI MOSFET's

Abstract: Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t/sub si/ region. The reasons for the mobility decrease have been examined from a device simulation and measurements. >

Low voltage SOI (silicon on insulator) logic circuit

Abstract: A SOI (Silicon On Insulator) logic circuit including serially connected power switching SOI MOSFETs (44, 45) and a logic circuit (43) constituted by SOI MOSFETs. The bodies of the MOSFETs of the logic circuit are made floating state, thereby implementing low threshold voltage MOSFETs. The bodies of the power switching MOSFETs are biased to power supply potentials, thereby implementing high threshold MOSFETs. The low threshold voltage MOSFETs enable the logic circuit to operate at a high speed in an active mode, and the high threshold voltage power switching MOSFETs can reduce the power dissipation in a sleep mode.

TFSOI complementary BiCMOS technology for low power applications

Abstract: A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 /spl mu/A is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 /spl mu/W 1 GHz prescaler circuit is demonstrated using this technology. >

Semiconductor device and method of manufacturing the same

Abstract: A method of manufacturing a semiconductor device includes a step of forming a device region 5 that is separated by a device-separation insulating film 4 formed in a part of an SOI layer, a step of forming a gate insulating film 6 a on a device region 5 so that the device region 5 can be exposed on both sides of the gate insulating film 6 a, a step of forming a gate electrode 7 a with polysilicon on the gate insulating film 6 a, a step of adjusting the area of exposed silicon so that the area of exposed silicon can be a prescribed area by forming at least either a pseudo region 5 b or a pseudo electrode 7 b to control the growth rate in growing an epitaxial layer 9 , and a step of conducting low-temperature epitaxial growth of silicon.

Approach to obtain high quality GaN on Si and SiC-on-silicon-on-insulator compliant substrate by molecular-beam epitaxy

Abstract: Crystalline SiC thin layers have been grown on 125 mm silicon‐on‐insulator (SOI) substrates as a promising and economical substrate for the growth of GaN epilayers. Through the use of an AlN/GaN strained superlattice buffer layer, high quality GaN layers as thin as 2000 A on Si(111) substrates have been achieved. X‐ray diffraction curves with a full width at half‐maximum (FWHM) as narrow as 25 arcmin were obtained. The associated low‐temperature photoluminescence (PL) spectrum showed a dominant bound‐exciton peak with a FWHM of 8 meV. We have further combined these two techniques to synthesize the first GaN on SiC on a SOI structure.

Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET's without self-heating

Abstract: A new method for measuring the output (I/sub D/-V/sub D/) characteristics of SOI MOSFET's without self-heating is described. The method uses short pulses with a low repetition rate, and a reverse transient loadline construction. The technique is demonstrated by measuring 0.25 /spl mu/m bulk and SOI MOSFET's with 5-nm gate oxide. Application of the method to the extraction of device temperature as a function of DC power is also illustrated. >

Programming and erase with floating-body for high density low voltage flash EEPROM fabricated on SOI wafers

Abstract: The new portable computing and telecommunications market requires high performance, low power, high density electrically reprogrammable non-volatile memories. Memories integrated with information handling circuits on SOI wafers can offer significant advantages for high speed computation, better isolation, lower leakage, better noise immunity, and excellent CMOS latch-up margin. A NOR Virtual Ground (NVG) flash memory cell fabricated on an SOI wafer is considered. The fabrication process for NVG on SOI can be unchanged if the silicon thickness of the SOI wafer is properly chosen and doped, such that the N+ bit-line (Source/Drain) touches the oxide layer. One important feature of cells on SOI is that it is difficult to ground the p-body of cell and it will be left floating during all memory operations. Therefore, it is important to study the effect of the floating body on channel-hot-electron (CHE) programming and Fowler-Nordheim (F-N) channel erase used in NVG flash memory.

SOI-type semiconductor device with suppressed spread of depletion region

Abstract: In a semiconductor device including a semiconductor substrate (1, 1'), an insulating layer (2) formed on the semiconductor substrate and a semiconductor layer (3) formed on the insulating layer, the impurity concentration of at least one part of the semiconductor substrate in the proximity of the insulating layer is rich, i.e., higher than that of the other part of the semiconductor substrate.

FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures

Abstract: A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

Scaling constraints imposed by self-heating in submicron SOI MOSFET's

Abstract: The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 18 V In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction >

Reduction of threshold voltage sensitivity in SOI MOSFET's

Abstract: The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V/sub th/ implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t/sub si/ examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity. >

Magnetic field detection

Abstract: A solid state triode employs the Hall effect to asymmetrically proportion flow of current through different branches of a number of cascaded bifurcated N- charge carrier channels (10,18,20), thereby providing an indication of strength and direction of an applied magnetic field by measuring magnitude and sense of the difference between currents flowing in the two channel branches (14,16,24,26,30,32). The solid state triode is formed on an silicon-on-insulator (SOI) substrate (47,48,49) in which an N+ source region (54) and at least two end N+ drain regions (56,58) are interconnected by an N- charge carrier channel (60) that is defined by a plurality of P+ regions (64a,64b,64c,64d) in a thin single crystal silicon substrate (49) between the source and drain regions (54,56,58). A polysilicon gate (52) overlies the N- channel and acts as a self-aligning mask during manufacture of the triode to precisely align the N+ and P+ doping to the polysilicon gate configuration. The SOI has a very thin N- doped layer to which the N+ and P+ doping is applied in steps of successively different energy levels so that the doping extends completely through the N- layer and is uniform throughout the thickness of the layer. The N- channel is narrow and has a width at least twice the thickness of the crystal silicon uppermost layer of the SOI substrate.

SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films

Abstract: The effects of scaling MESA isolated (with sidewall reoxidation) SOI MOSFETs with respect to channel length, channel width, silicon film thickness and buried oxide thickness have been studied experimentally. Characteristics of narrow-width devices have a strong dependence on T/sub Si/. In devices with small T/sub Si/, narrow-width effect dominates over short channel effect. Thin buried oxide reduces self-heating and short channel effect, but results in a lower intrinsic current drive due to the effect of backside coupling. The trade-offs and limitations for scaling individual dimension in MESA isolated SOI MOSFETs are discussed.

An AC conductance technique for measuring self-heating in SOI MOSFET's

Abstract: In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFET's from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFET's that demonstrate that heating can indeed be significant in SOI devices. >

Semiconductor pressure sensor

Abstract: PURPOSE:To detect a failure of an insulating layer and to prevent the insulating layer from breakdown even if a high voltage is applied when a pressure sensor chip is anode-junctioned to glass pedestals by a method wherein strain detecting elements of a SOI structure are provided at diaphragm correspondence parts provided on a silicon substrate and an electrode, which is connected to the substrate, is provided on the side of the surfaces of the strain detecting elements. CONSTITUTION:An aluminium electrode film 6, which is connected to a silicon substrate 1, is provided. Therefore, when an inspection of strain detecting elements 3 is made, the good or bad of an insulating layer provided for the strain detecting elements on the substrate 1 is detected so as to be able to detect easily by measuring insulation resistances between the film 6 connected to the substrate 1 and electrode films 4 of the elements 3. Moreover, when pedestals 18 are anode-junctioned to a pressure sensor chip 18, a voltage is applied in such a way that its is applied from the film 6 connected to the substrate 1 and as a potential difference is prevented from being generated in the substrate 1 via the elements 3 and the insulating layer 2, the dielectric breakdown of the layer 2 can be prevented from being caused and a stable and accurate pressure measurement can be executed to noise and static electricity.

Silicon-on-insulator gate-all-around mosfet fabrication methods

Abstract: A silicon-on-insulator (SOI) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by a top gate and a buried bottom gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which was formed on source, channel and drain semiconductor layer of an SOI wafer. After forming a planar bottom insulator layer on the bottom gate and bottom gate dielectric, the SOI wafer is flip-bonded onto an oxide layer of a bulk silicon wafer, thereby encapsulating the buried bottom gate electrode in insulating oxide, after which the SOI substrate and the etch-stop SOI oxide layer are removed to expose the SOI semiconductor layer which is processed to form the source, drain and channel in a mesa structure on which is deposited a top gate dielectric, a top gate, and top gate insulator as well as four conductors for connecting to the source, drain, top gate and bottom gate. The latter two electrodes can be independently controlled or commonly controlled for enhanced operation of GAA MOSFET having improved isolation and reduced parasitic capacitance due to the use of encapsulating insulation layers of the merged wafer consisting of the bonded SOI wafer and bulk silicon wafer.

Single-etch stop process for the manufacture of silicon-on-insulator substrates

Abstract: A single-etch stop process for the manufacture of silicon-on-insulator substrates The process includes forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 05 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18 boron atoms/cm 3 and a resistivity of about 001 to about 002 ohm-cm A portion of the device wafer is mechanically removed from the silicon-on-insulator bonded substrate wherein the device wafer has a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the mechanical removal step The defect-free surface of the device wafer is thereafter etched away to expose the device layer, and the exposed device layer is polished to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer