Showing papers on "Silicon on insulator published in 1996"

Silicon-based visible light-emitting devices integrated into microelectronic circuits

Abstract: MICROELECTRONIC device integration has progressed to the point where complete 'systems-on-a-chip' have been realized1–3. Now that optoelectronics is becoming increasingly important for information and communication technologies, there is a need to develop optoelectronic devices that can be integrated with standard microelectronics. Conventional semiconductor technology is largely based on crystalline silicon, which (being an indirect bandgap semiconductor) is an inefficient light-emitting material. This has stimulated significant effort towards developing silicon-based optoelectronic components and, of the several strategies explored so far4,5, the use of porous silicon appears the most promising; porous silicon produces high-efficiency, room-temperature, visible photoluminescence6, and its material and optical properties have been studied in detail7,8. But the extreme reactivity and fragility of porous silicon have hitherto prevented its integration with conventional silicon processing technology. We have recently shown9,10 that the thermal and chemical stability of porous silicon can be greatly enhanced — while retaining desirable light-emitting and charge-transport properties — by partial oxidation. Here we take advantage of these improvements in material properties to demonstrate the successful integration of silicon-based visible light-emitting devices into a standard bipolar microelectronic circuit.

Absorption enhancement in silicon‐on‐insulator waveguides using metal island films

Abstract: We report the degree to which the resonances associated with metal island films can be used to enhance the sensitivity of very thin semiconductor photodetectors. The island films can couple incident light into the waveguide modes of the detector, resulting in increased absorption. To characterize the coupling, silver‐, gold‐, and copper‐island layers were formed on the surface of a thin‐film photodetector fabricated in the 0.16 μm thick silicon layer of a silicon‐on‐insulator (SOI) wafer. The copper islands gave the best result, producing more than an order of magnitude enhancement in the photocurrent for light of wavelength 800 nm. The enhancements appear to be due primarily to coupling between the metal island resonances and the waveguide modes supported by the SOI structure.

Application of hydrogen ion beams to Silicon On Insulator material technology

Abstract: A new application for proton ion beams in the field of Silicon On Insulator material (SOI) technology is reported. In this technology, based on hydrophillic wafer bonding and referred to as “Smart-Cut”, heat treatment induces an in-depth micro-slicing of one of two bonded wafers previously implanted with hydrogen. The principle of this process involves the basic mechanisms associated with high fluence proton implantation in materials, such as blistering, flaking and exfoliation. The intrinsic properties of this process lead to very high crystalline quality of the SOI layers and very good thickness uniformity. After presentation of the process details and the underlying physical aspects, the main characteristics of the Smart-Cut technology and first physical and electrical characterizations are reported.

Coulomb blockade oscillations at room temperature in a Si quantum wire metal‐oxide‐semiconductor field‐effect transistor fabricated by anisotropic etching on a silicon‐on‐insulator substrate

Abstract: We have developed a very controllable fabrication process of an extremely narrow (∼10 nm) quantum wire metal‐oxide‐semiconductor field‐effect transistor (MOSFET) on a separation‐by‐implanted‐oxygen (SIMOX) substrate using anisotropic etching and selective oxidation technique. The drain current versus gate voltage characteristics show oscillations caused by Coulomb blockade even at room temperature. The oscillations split into several sharp peaks when the temperature is decreased, indicating that the channel is separated by several serial coupled quantum dots and that the quantum levels of these dots correspond to the observed fine peaks.

Production of substrate for tensilely strained semiconductor

Abstract: A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Silicon carbide on insulator formation using the Smart Cut process

Abstract: The Smart Cut process has been applied for the first time to SiC, in order to form silicon carbide on insulator (SiCOI) structures. These structures have been formed on polycristalline SiC and on silicon substrates.

ased Methodology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of a Silicon-on-Insulator

Abstract: A new design methodology based on a unified treat- ment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over dc drain current gm/ID and the normalized current Io /( W/L). The gm /ID indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

Transfer of structured and patterned thin silicon films using the smart-cut process

Abstract: The feasibility of transferring patterned and multilayered thin films, simulating part of the stacked structure of a CMOS integrated circuit, from their original bulk silicon substrate to a final substrate, was demonstrated using the Smart-Cut process.

Single-event effects in SOI technologies and devices

Abstract: Due to their limited sensitive volumes for charge collection, silicon on insulator (SOI) technologies are good candidates for any microelectronic device operating in a space environment. While being insensitive to latchup phenomena, SOI devices may experience single-event effects (SEE's). Based on the analysis of the various structures of SOI transistors, charge collection mechanisms are presented. The different models proposed to analyze the sensitivity of CMOS SRAM cells are then discussed. The available data of SEU characterizations are finally compiled.

Single-etch stop process for the manufacture of silicon-on-insulator wafers

Abstract: A single-etch stop process for the manufacture of silicon-on-insulator wafers. The process includes forming a silicon-on-insulator bonded wafers comprising a substrate layer (26), an oxide layer (28), a device layer (22), and a device wafer (20). The device layer (22) is situated between the device wafer (20) and the oxide layer (28) and the oxide layer (28) is between the device layer (22) and the substrate layer (26). The device wafer (20) has a p+ or n+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm. A portion of the device wafer (20) is removed from the silicon-on-insulator bonded wafers and the remaining portion of the device wafer (20) has a defect-free surface after such removal. The remaining portion of the device wafer (20) is then etched to expose the device layer (22).

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

Abstract: This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.

Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications

Abstract: A body-coupled gated diode for silicon-on-insulator (SOI) technology is disclosed. The body-coupled gated diode is formed from an SOI field-effect transistor (FET). The body, gate and drain of the SOI FET are tied together, forming the first terminal of the diode. The source of the SOI FET forms the second terminal of the diode. Both NFETs and PFETs may be used to create the diode. An SOI circuit comprising at least one body-coupled gated diode formed from the SOI FET provides electrostatic discharge (ESD) protection and ideal diode characteristics.

A VLSI-compatible high-speed silicon photodetector for optical data link applications

Abstract: A novel silicon photodetector suitable for high-speed, low-voltage operation at 780- to 850-nm wavelengths is reported. It consists of an interdigitated p-i-n detector fabricated on a silicon-on-insulator (SOI) substrate by using a standard bipolar process. Biased at 3.5 V, this device attains a -3-dB bandwidth in excess of 1 GHz at /spl lambda/=840 nm. The dc responsivity measured at /spl lambda/=840 nm on nonoptimized structures ranges from 0.05 to 0.09 A/W, depending on the finger shadowing factor. A new approach for improving the responsivity is proposed and quantitatively analyzed. The fabricated devices exhibit extremely low dark currents, small capacitance, large dynamic range, and no evidence of low-frequency gain. The overall performance and process compatibility of these photodetectors make them viable candidates for the fabrication of silicon monolithic receivers for fiber-optic data links.

Semiconductor memory device having peripheral circuit and interface circuit fabricated on bulk region out of silicon-on-insulator region for memory cells

Abstract: A semiconductor dynamic random access memory device has a memory cell array (31) fabricated on a silicon-on-insulator region (30a) and peripheral and interface circuits (32/33) fabricated on a bulk region (30b); even if the circuit components of the peripheral circuit (32) are increased together with the memory cells, the bulk region (30b) effectively radiates the heat generated by the peripheral and interface circuits (32/33), thereby preventing the memory cells from a temperature rise.

Silicon on insulator (SOI) dram cell structure and process

Abstract: A silicon on insulator (SOI) DRAM has a layer of buried oxide covered by a thin layer of crystalline silicon on the surface of a bulk silicon substrate Field oxide regions are formed extending through the thin crystalline silicon surface layer and into contact with the buried oxide layer Gate oxide layers, gate electrodes and source/drain regions for the transfer FETs of the DRAM are formed in and on the thin crystalline silicon surface layer in the active regions between the field oxide regions A trench is opened through one of the source/drain regions of each of the transfer FETs A layer of doped polysilicon is provided to line the trenches and is patterned to form at least a part of the bottom electrodes of the charge storage capacitors for the DRAM The bottom electrodes are covered with a thin dielectric layer and an upper electrode of doped polysilicon is provided Preferably, the trench for the bottom capacitor electrode extends through the buried oxide layer and may extend into the bulk silicon

Integrated optics in silicon and SiGe-heterostructures

Abstract: This paper reviews various techniques and ideas in the field of integrated optics in silicon, mainly focused on silicon in conjunction with germanium. We will discuss different approaches for waveguides, passive and active components in silicon as well as recent developments in the fabrication and performance of such components. For waveguides in silicon, the characteristics such as losses and spot-sizes are given, showing that silicon could be an attractive candidate for integrated optical devices.

SOI-type semiconductor device with variable threshold voltages

Abstract: In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an active mode A ground voltage is applied to back gates of N-channel MOS transistors in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel MOS transistors in an active mode

Method for manufacturing a vertical transistor having a storage node vertical transistor

Abstract: A method for manufacturing a three-dimensionally structured vertical transistor or memory cell including the steps of forming a silicon-on-insulator (SOI) structure on a semiconductor substrate, sequentially depositing a drain region, a channel region and a source region on the SOI substrate structure, a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, to thereby increase the integration of a device. This process and structure avoids the characteristic degradation caused by the leakage current associated with the trench process and structure.

Applications of Aluminium Nitride Films Deposited by Reactive Sputtering to Silicon-On-Insulator Materials

Abstract: Self-heating effects in silicon-on-insulator (SOI) devices limit the applicability of SOI materials in electronics in cases where high power dissipation is expected. Aluminium nitride as a potential candidate for buried insulator material in future SOI-structures is investigated. Reactive sputtering was used to manufacture the aluminium nitride films. The deposited films exhibit low stress and fairly low surface roughness. Further, resistivities above 1014 Ωcm as well as low thermal resistances were obtained. Interfacial problems at the interface between silicon and aluminium nitride were handled by adding a thin (a few nm) film of thermally grown silicon dioxide to that interface. The deposited films could be bonded both directly and through an electrostatic technique to silicon wafers. The presented results show that it is possible to make SOI structures with aluminium nitride as buried insulator by means of wafer bonding and subsequent etch-back.

Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach

Abstract: This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices.

Method of making back gate contact for silicon on insulator technology

Abstract: A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.

Method for silicon island formation

Abstract: A method is disclosed of manufacturing improved device structures which include a device structure having STI and a thin foot charge drain beneath the device area on an inexpensive bulk silicon substrate. The structures retain high speed operation of SOI devices without any adverse effects of charge build-up and floating effects as observed in conventional SOI devices, and, furthermore, are constructed without any extra process steps added to the conventional STI technology except for an isotropic etching step. The invention also contemplates construction of multi-level electronic circuit. In various embodiments, the invention includes steps of forming a photoresist pattern over a semiconductor substrate to designate a plurality of islands, anisotropic etching the substrate to form plurality of designate islands which develops thin passivation layer on the sidewall, performing successively an isotropic etching on the resulting structure to create a thin foot region under each of the plurality of the islands with the help of the passivation layer, and forming a thin thermal oxide layer to improve the interface quality between each thin foot region and the insulator. Additional layers of silicon islands may be formed on the resulting structure.

Cmos circuitry with shortened p-channel length on ultrathin silicon on insulator

Abstract: An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.

A silicon-on-insulator quantum wire

Abstract: Thin, narrow silicon-on-insulator n-channel MOSFETs have been fabricated. The drain current characteristics, when measured as a function of gate voltage at low temperature, exhibit a series of oscillations, which is characteristic of current transport in one-dimensional systems (quantum wires). Theoretical calculation of the current oscillations in the device show reasonable agreement with the experimental characteristics.

Comparison of microwave inductors fabricated on silicon-on-sapphire and bulk silicon

Abstract: Inductors are important elements of microwave circuits that frequently require high self-resonant frequencies and high quality factors. In this work, circular spiral inductors fabricated on silicon-on-sapphire (SOS) and bulk silicon are compared. Due to the low-loss dielectric substrate, SOS inductors showed both higher self-resonant frequencies and higher quality factors than those fabricated on bulk silicon. Small-signal models extracted for the inductors confirm that the degradation of the inductor characteristics in bulk silicon stems from losses in the substrate.

Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits

Abstract: Transistor models which reproduce the superior device characteristics of fully depleted silicon-on-insulator (SOI) MOSFETs and which are efficient for the design of analogue CMOS circuits are discussed and validated. These analogue models are then used to investigate the significant performance improvement that several basic analogue cells can achieve when optimized in fully depleted SOI CMOS, rather than in bulk CMOS technology. Experimental verifications support this original demonstration of the great potential of fully depleted SOI CMOS for low voltage, low power analogue applications.

Compact self-aligned body contact silicon-on-insulator transistor

Abstract: A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.

Self-aligned edge control in silicon on insulator

Abstract: An improved process and structure for channel stop in silicon on insulator using LOCOS isolation are disclosed. Advantages include decreased ion dose requirements; reduced processing time; smaller ΔW characteristics, thus, small transistor size and more precise process control over the edge of a MOSFET. the process also makes possible a wide range of transistor design capabilities and improved transistor operating parameters.

MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates

Abstract: A MOS transistor formed in a silicon on insulator structure includes a rectifying connection between a body portion and the gate. The connection decreases the threshold voltage of the transistor in the reverse bias state and limits a difference in voltage between the body and gate in the forward bias state of the rectifying contact.

A low-voltage, low-power microwave SOI MOSFET

Abstract: Summary form only given. Recently, it has been demonstrated that the use of high-resistivity SOI (SIMOX) substrates (5,000 and 10,000 /spl Omega/.cm) yields MOSFETs which offer interesting microwave performances. Indeed unity-gain frequencies (f/sub T/) of 14 and 23.6 GHz and maximum oscillation frequencies (f/sub max/) of 21 and 32 GHz have been reported for effective gate lengths of 0.36 and 0.25 /spl mu/m, respectively, and using supply voltages ranging from 3 to 5 volts. Such devices can be integrated with planar lines to implement MMIC circuits. These transistors were fabricated using a dedicated MOS process, called MICROX/sup TM/, which uses non-standard CMOS features, such as a metal (gold) gate and air-bridge metallisation. In this work, the high-frequency performances of microwave transistors fabricated using a standard fully-depleted SOI CMOS process are described. These devices are, therefore, compatible with analog and digital circuits fabricated using the same low-cost process.