Showing papers on "Silicon on insulator published in 1999"

Phonon scattering in silicon films with thickness of order 100 nm

Abstract: Although progress has been made in the ab initio simulation of lattice dynamics in semiconducting crystals, information about the relaxation of nonequilibrium lattice vibrations remains incomplete. This work studies the relaxation times of room-temperature thermal phonons through measurements of thermal conduction along monocrystalline silicon films of thickness down to 74 nm. A repetitive oxidation and etching process ensures that the purity and crystalline quality of the films are comparable with those of bulk samples. Phonon-interface scattering reduces the thermal conductivity by up to 50% at room temperature. The data indicate that the effective mean-free path of the dominant phonons at room temperature is close to 300 nm and thus much longer than the value of 43 nm predicted when phonon dispersion is neglected. This study indicates that a broad variety of lattice transport characteristics for bulk silicon can be obtained through measurements on carefully prepared silicon nanostructures. The present data are also valuable for the thermal simulation of silicon-on-insulator (SOI) transistors.

Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby

Abstract: A gallium nitride microelectronic layer is fabricated by converting a surface of a (111) silicon layer to 3C-silicon carbide. A layer of 3C-silicon carbide is then epitaxially grown on the converted surface of the (111) silicon layer. A layer of 2H-gallium nitride then is grown on the epitaxially grown layer of 3C-silicon carbide. The layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer. In one embodiment, the silicon layer is a (111) silicon substrate, the surface of which is converted to 3C-silicon carbide. In another embodiment, the (111) silicon layer is part of a Separation by IMplanted OXygen (SIMOX) silicon substrate which includes a layer of implanted oxygen that defines the (111) layer on the (111) silicon substrate. In yet another embodiment, the (111) silicon layer is a portion of a Silicon-On-Insulator (SOI) substrate in which a (111) silicon layer is bonded to a substrate. Lateral growth of the layer of 2H-gallium nitride may be performed by Epitaxial Lateral Overgrowth (ELO) wherein a mask is formed on the layer of 2H-gallium nitride, the mask including at least one opening that exposes the layer of 2H-gallium nitride. The layer of 2H-gallium nitride then is laterally grown through the at least one opening and onto the mask. A second, offset mask also may be formed on the laterally grown layer of 2H-gallium nitride and a second laterally grown layer of 2H-gallium nitride may be overgrown onto the offset mask. Lateral growth of the layer of 2H-gallium nitride also may be performed using pendeoepitaxial techniques wherein at least one trench and/or post is formed in a layer of 2H-gallium nitride to define at least one sidewall therein. The layer of 2H-gallium nitride is then laterally grown from the at least one sidewall. Pendeoepitaxial lateral growth preferably continues until the laterally grown sidewalls coalesce on the top of the posts or trenches. The top of the posts and/or the trench floors may be masked to promote lateral growth and reduce nucleation and vertical growth.

Silicon interposer and multi-chip-module (MCM) with through substrate vias

Abstract: An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate. The silicon substrate may have a via. The package may further include a solder bump that is attached to both the integrated circuit and the silicon subtstrate. The silicon substrate has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated circuit.

Surface roughness at the Si–SiO2 interfaces in fully depleted silicon-on-insulator inversion layers

Abstract: The effect of surface roughness scattering on electron transport properties in extremely thin silicon-on-insulator inversion layers is carefully analyzed. It is shown that if the silicon layer is thin enough (thinner than 10 nm) the presence of the buried interface plays a very important role, both by modifying the surface roughness scattering rate due to the gate interface, and by itself providing a non-negligible scattering rate. The usual surface roughness scattering model in bulk silicon inversion layers is shown to overestimate the effect of the surface-roughness scattering due to the gate interface as a consequence of the minimal thickness of the silicon layer. In order to account for this effect, an improved model is provided. The proposed model allows the evaluation of the surface roughness scattering rate due to both the gate interface and the buried interface. Once the scattering rates are evaluated, electron mobility is calculated by the Monte Carlo method. The effect of the buried interface ro...

Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same

Abstract: A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Silicon-on-insulator vertical array device trench capacitor DRAM

Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

Layered dielectric on silicon carbide semiconductor structures

Abstract: A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on the silicon dioxide layer, with the insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide, and a gate contact to the insulating material. In other devices the dielectric structure forms an enhanced passivation layer or field insulator.

Monolithic CMOS distributed amplifier and oscillator

Abstract: CMOS implementations for RF applications often employ technology modifications to reduce the silicon substrate loss at high frequencies. The most common techniques include the use of a high-resistivity substrate (/spl rho/>10 /spl Omega/-cm) or silicon-on-insulator (SOI) substrate and precise bondwire inductors. However, these techniques are incompatible with low-cost CMOS manufacture. This design demonstrates use of CMOS with a conventional low-resistivity epi-substrate and on-chip inductors for applications above 10 GHz.

The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling

Abstract: This paper discusses state-of-the-art electrostatic discharge (ESD) protection in advanced semiconductor technologies and emerging technologies. ESD physics, semiconductor process issues, device and circuit simulation, circuits, and devices are examined.

Method for fabricating a hybrid optical integrated circuit employing SOI optical waveguide

Abstract: The present invention relates to an optical integrated circuit; and, more particularly, to a method for preparing an improved hybrid optical integrated circuit which is capable of accommodating optical waveguides, optical devices, such as light emitting devices and light receiving devices, and optical fibers in an effective manner. The present invention has the advantages of minimizing horizontal misalignment error between the SOI waveguide rib area, the V-groove etch window and the alignment marks, decreasing the manufacturing cost by passively aligning the waveguides, the optical devices and the optical fibers on a single substrate. Also, the present invention has an effect of reducing fresnel reflection loss by providing the LPCVD silicon nitride layer capable of being used as an anti-reflection coating layer at both ends of the waveguide.

SON (silicon on nothing)-a new device architecture for the ULSI era

Abstract: A novel device architecture called SON (silicon on nothing) is proposed, allowing extremely thin buried oxides and silicon films to be fabricated and thereby provide better resistance to short channel effects (SCE) and DIBL than any other device architecture. SON devices are shown to present excellent I/sub on//I/sub off/ trade-off, V/sub th/ roll-off suppression down to 15 nm channel length, and to be free from the shortcomings of conventional SOI, such as self-heating, high S/D series resistances, and expensive SOI substrates since SON devices are fabricated on bulk silicon.

Silicon compatible materials for harsh environment sensors

Abstract: The wide bandgap semiconductors silicon carbide and diamond and the material system Silicon On Insulator (SOI) are compared regarding their suitability as silicon compatible materials to extend the application fields of micromachined sensors to harsh environment conditions especially to high temperatures. The harsh environment conditions are specified by analyzing the demands of automotive and aerospace applications. The physical properties of the material systems are discussed and their technological stage of development is evaluated, especially with respect to the compatibility to standard silicon processes. Furthermore, the commercial availability of the different materials in the form of substrates is considered and a forecast of future developments is attempted. As an example of a harsh environment sensor, a combustion pressure sensor is presented and characterized.

Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor

Abstract: A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.

Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices

Abstract: A numerical model for obtaining linear doping profiles in the drift region of high-voltage thin-film SOI devices is proposed and experimentally verified. Breakdown voltage in excess of 612 V on LDMOS transistors with 0.15-/spl mu/m SOI layer, 2-/spl mu/m buried oxide, and 50-/spl mu/m drift region is designed and demonstrated using this model. Theoretical and experimental dependence of the breakdown voltage on the drift region length are compared. Good agreement between the simulation and experimental results are obtained. Dependence of the breakdown voltage on the doping density and doping concentration slope in the linearly doped drift region is also investigated experimentally. Results indicate that an optimum concentration slope is needed in order to optimize the breakdown voltage in the thin-film SOI devices with a linear doping drift region. Finally, a 600-V CMOS compatible thin-film SOI LDMOS process is also described.

Semiconductor device having SOI structure and manufacturing method thereof

Abstract: A semiconductor device with a SOI structure comprises; a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film; second conductivity type source and drain regions formed in the surface semiconductor layer; and a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film, wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and which is adjacent to the buried insulating film.

Partially-depleted SOI technology for digital logic

Abstract: This partially-depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology. A number of SOI-unique effects that complicate device and circuit design are discussed, along with possible remedies. A fully functional 32 bit microprocessor, operating at >500 MHz, demonstrates this SOI technology.

Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization

Abstract: Metal-induced-lateral-crystallization (MILC) followed by high temperature annealing has been used for the first time to form, large single grain silicon from amorphous silicon. Polysilicon with grain size ranging from ten to hundred of microns can be formed by this method. By individually crystallizing the active area of a TFT, the entire transistor can be formed on a single or a small number of silicon grains with good controllability, thus similar to SOI structure. Test devices with thin t/sub ox/=120 /spl Aring/ have been fabricated and the performance is verified to be comparable to SOI MOSFETs. The scaling property of the grain enhanced TFTs has also been studied. The minimization of the device dimension results in smaller probability for the channel region of a TFT to cover multiple grains, which leads to better device performance.

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

Abstract: This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

Abstract: A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

Abstract: This paper presents for the first time, multiple layers of silicon-on-insulator (MLSOI) device islands fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) techniques. MLSOI has the potential for ultra dense device integration. SOI device islands as small as 150 nm/spl times/150 nm, with thickness down to 40 nm have been fabricated. SOI device islands (5 /spl mu/m/spl times/500 /spl mu/m) in the second layer have shown no stacking faults in the 1290 islands inspected. To demonstrate the device quality material, fully depleted SOI (FD-SOI) P-MOSFET's were fabricated in the first layer SOI islands with gate lengths down to less than 170 nm. Typically they had low subthreshold leakage, below 0.2 pA//spl mu/m, and a subthreshold swing of 76 mV/dec was measured.

SOI FET body contact structure

Abstract: A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

On the origin of tunneling barriers in silicon single electron and single hole transistors

Abstract: To clarify the channel potential profiles, Coulomb blockades of single electron and single hole tunneling in Si nanosize narrow channel metal–oxide–semiconductor field-effect transistors are intensively studied. Devices with both n+ and p+ source/drain contacts were fabricated on silicon-on-insulator substrates. Transport properties of a hole system as well as an electron system induced in the same channel were investigated. It is found from the experimental results that potential fluctuations in the channel act as tunnel barriers for both electrons and holes. Lateral quantum confinement effects or silicon oxide (SiOx) are thought to be the cause of tunnel barriers.

High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits

Abstract: An exhaustive experimental study of the high-frequency noise properties of MOSFET in silicon-on-insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length, gate finger width, and gate sheet resistivity on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching condition is demonstrated. From experimental results, optimal ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low-noise amplifiers for multigigahertz portable communication systems is shown.

Method for fabricating a high-density semiconductor memory device

Abstract: A method for fabricating a high-density semiconductor memory device which can reduce chip size and increase memory device characteristics. The present invention provides SOI type memory device. The capacitor is embedded in the insulator below the semiconductor wafer and the transistor is formed after the formation of the capacitor. As a result, the degradation of the transistor can be prevented, sufficiently increase the capacitor surface area, and provide fully planarized surface during the processing steps.

Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region. In order to provide improved breakdown voltage characteristics, a dielectric layer is provided over at least a part of the insulation region and the gate electrode, and a field plate electrode is provided over at least a part of the dielectric layer which is in direct contact with the insulation region, with the field plate electrode being connected to an electrode of the lateral transistor device.

Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer

Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Silicon-on-insulator devices and method for producing the same

Abstract: A process of producing controllable thicknesses of silicon-on-insulator (SOI) for fully-depleted double-gate applications is provided. The process comprises depositing an oxide layer on a silicon wafer, depositing a nitride layer of a controlled thickness on the oxide layer, etching the nitride layer to open a first trench of controlled thickness, opening a second trench down to the silicon substrate, growing epitaxial silicon using epitaxial lateral overgrowth (ELO) to fill the second trench and grow sideways to fill the first trench, perform planarization of ELO silicon using the nitride layer as a chemical-mechanical polishing (CMP) stop layer, and fabricating a SOI device in the first trench.

Coulomb blockade in quasimetallic silicon-on-insulator nanowires

Abstract: Using highly doped silicon-on-insulator (SOI) films, we demonstrate metallic Coulomb blockade in silicon nanowires at temperatures up to almost 100 K. We propose a process that leads to island formation inside the wire due to a combination of structural roughness and segregation effects during thermal oxidation. Hence, no narrowing of the SOI wire is necessary to form tunneling contacts to the single-electron transistors.

BUSFET-a radiation-hardened SOI transistor

Abstract: The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are 1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or 2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. We call this structure the BUSFET-Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source.

A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration

Abstract: A new technique to form empty spaces in silicon substrates is presented. The empty space with various shapes, such as plate as well as sphere and pipe, could be formed under the surface of the silicon substrate.