Showing papers on "Silicon on insulator published in 2003"

Nanophotonic waveguides in silicon-on-insulator fabricated with CMOS technology

Abstract: High-index-contrast, wavelength-scale structures are key to ultracompact integration of photonic integrated circuits. The fabrication of these nanophotonic structures in silicon-on-insulator using complementary metal-oxide-semiconductor processing techniques, including deep ultraviolet lithography, was studied. It is concluded that this technology is capable of commercially manufacturing nanophotonic integrated circuits. The possibilities of photonic wires and photonic-crystal waveguides for photonic integration are compared. It is shown that, with similar fabrication techniques, photonic wires perform at least an order of magnitude better than photonic-crystal waveguides with respect to propagation losses. Measurements indicate propagation losses as low as 0.24 dB/mm for photonic wires but 7.5 dB/mm for photonic-crystal waveguides.

Frontiers of silicon-on-insulator

Abstract: Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

High performance fully-depleted tri-gate CMOS transistors

Abstract: Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

Radiation effects in SOI technologies

Abstract: Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Extremely scaled silicon nano-CMOS devices

Abstract: Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Influence of device engineering on the analog and RF performances of SOI MOSFETs

Abstract: This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

Abstract: A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.

Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 106cm2. The approach begins with the growth of a pseudomorphic or nearlypseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operatiing with this method is dislocation nucleation at He-inducedplatelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

High mobility heterojunction complementary field effect transistors and methods thereof

Abstract: A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.

Electrooptic modulation of silicon-on-insulator submicrometer-size waveguide devices

Abstract: In this paper, we propose and analyze an electrically modulated silicon-on-insulator (SOI) submicrometer-size high-index-contrast waveguide. The geometry of the waveguide provides high lateral optical confinement and defines a lateral p-i-n diode. The electrooptic structure is electrically and optically modeled. The effect of the waveguide geometry on the device performance is studied. Our calculations indicate that this scheme can be used to implement submicrometer high-index-contrast waveguide active devices on SOI. As an example of application, a one-dimensional microcavity intensity modulator is predicted to exhibit a modulation depth as high as 80% by employing a dc power consumption as low as 14 /spl mu/W.

SOI substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the SOI substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus

Abstract: An SOI (Silicon On Insulator) substrate is provided with: a support substrate ( 201 ); a single crystal silicon layer ( 202 ) disposed above one surface of the support substrate; an insulation portion ( 205 ) disposed between the support substrate and the single crystal silicon layer, the insulation portion comprising a single layer of an insulation film or a lamination structure of a plurality of insulation films, and including a silicon nitride film or a silicon nitride oxide film ( 204 ).

Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

Abstract: In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T/sub SI/) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T/sub SI/ fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T/sub SI/ fluctuation scattering are remarkably enhanced with reducing T/sub SI/, so that they could help explain the experimental mobility behavior.

Double-gate FinFET device and fabricating method thereof

Abstract: The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction. The conventional double-gate MOS devices are fabricated using SOI wafers which are more expensive than bulk silicon wafers. It also has problems including the floating body effects, larger source/drain parasitic resistance, off-current increase, and deterioration in heat transfer to the substrate.

Semiconductor device and manufacturing method thereof

Abstract: The present invention provides: a high performance double gate SOI-MOS fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner, and furthermore, by isolating completely the buried electrodes electrically from each other, and the manufacturing method thereof It has the following features that a multi-layered SOI substrate having an amorphous or polycrystalline semiconductor layer constituted by way of a buried gate insulative film to a lower portion of an SOI layer is used, ion implantation is applied to the semiconductor layer in a pattern opposite to the upper gate electrode and the buried gate is constituted in a self-alignment relation with the upper gate

Semiconductor device fabrication method

Abstract: A reduction of a leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device. To this end, a silicon oxide film and a silicon nitride film are formed on a substrate, which is then heated to a temperature within a range of 20° C.-600° C. so that a plasma nitridation process can be performed on the silicon nitride film. Further, a thermal process is performed in a non-oxide gas atmosphere. By performing these processes, the gate leakage current can be significantly reduced in the formed gate insulator, and the silicon oxide-equivalent thickness of the insulating film can be significantly decreased as well.

Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device

Abstract: A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained.

Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal–oxide–semiconductor field-effect transistors

Abstract: We demonstrate that carrier scattering induced by the thickness fluctuation of a silicon-on-insulator (SOI) film reduces electron mobility in ultrathin-body metal–oxide–semiconductor field-effect transistors with SOI thickness, TSOI, of less than 4 nm at room temperature and is the dominant scattering mechanism at low temperatures. The thickness fluctuation of a nanoscaled SOI film induces large potential variations due to the difference of quantum-confinement effects from one part to another, and thus carrier scattering potentials are formed in the channel. It is shown that experimental electron mobility follows the theoretical TSOI dependence and the expected temperature dependence of the scattering induced by SOI thickness fluctuation.

Low-loss submicrometer silicon-on-insulator rib waveguides and corner mirrors.

Abstract: Rib microwaveguides are demonstrated on silicon-on-insulator substrates with Si film thickness of either 380 or 200 nm and a width of 1μm . Corner mirrors that allow compact 90° turns between two perpendicular waveguides are characterized. Measured propagation losses are ~0.4 dB/cm and ~0.5 dB/cm for 380-nm and 200-nm Si film, respectively, and mirror losses are ~1 dB . This allows the development of applications such as optical interconnects in integrated circuits over propagation distances larger than several centimeters.

Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

Asymmetrically coupled silicon-on-insulator microring resonators for compact add-drop multiplexers

Abstract: We report on improved filter characteristics of microring resonators (MRs) used as add-drop multiplexers for integrated photonic circuits. By introducing an asymmetrical coupling of the signal waveguides to the resonator, a higher throughput attenuation and drop efficiency is attained. The throughput attenuation is the decisive property for the application of microrings in photonic networks since it determines the crosstalk between drop signal and add signal at the throughput channel of an add-drop multiplexer. Experimental results are compared with analytical relations. MRs with a free-spectral range of 24 nm are fabricated on silicon-on-insulator substrates. A crosstalk reduction by 8.8 dB due to asymmetrical coupling is demonstrated.

Light-sensing device

Abstract: A method of fabricating light-sensing devices including photodiodes monolithically integrated with CMOS devices. Several types of photodiode devices (PIN, HIP) are epitaxially grown in one single step on active areas implanted in a common semiconductor substrate, the active areas having defined polarities. The epitaxially grown layers for the photodiode devices may be either undoped or in-situ doped with profiles suitable for their respective operation. With appropriate choice of substrate materials, device layers and heterojunction engineering and process architecture, it is possible to fabricate silicon­based and germanium-based multi-spectral sensors that can deliver pixel density and cost of fabrication comparable to the state of the art CCDs and CMOS image sensors. The method can be implemented with epitaxially deposited films on the following substrates: Silicon Bulk, Thick-Film and Thin-Film Silicon-On-Insulator (SOI), Germanium Bulk, Thick-Film and Thin-Film Germanium-On-Insulator (GeOI).

Self-aligned triple gate silicon-on-insulator (SOI) device

Abstract: A self-aligned transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region. Also disclosed is a method for manufacturing a transistor device. The method for manufacturing includes the steps of: providing a substrate having a buried oxide region; depositing a first nitride mask layer having a pattern overlying a silicon region; forming a trench in said substrate with a depth to said buried oxide; depositing a conformal oxide in said trench; forming vias in said conformal oxide adjacent to said silicon region and removing a portion of said first nitride mask to expose a portion of said silicon region; depositing polysilicon in said vias and on said portion of said silicon region; and implanting an impurity into exposed portions of polysilicon in said trench and of said silicon-on-insulator substrate underlying said second nitride layer.

Chapter 6 – Silicon on Insulator: Technology and Devices

Abstract: Publisher Summary Silicon on insulator (SOI) technology was conceived in the 1960s for the niche of radiation-hard circuits. A variety of SOI materials are invented in order to dielectrically separate the active device volume from the silicon substrate, using a buried oxide (BOX). The background idea is that, in a bulk silicon MOS transistor, only the superficial layer is useful for electron transport and device operation, whereas the substrate is responsible for undesirable, parasitic effects. The aim of this chapter is to overview the state-of-the-art of SOI technologies, starting with the key advantages of SOI circuits. Further describes the synthesis of the major SOI materials. The configuration and performance of typical devices are also evoked. The physical mechanisms involved in the operation of fully depleted and partially depleted SOI MOSFETs are discussed. An SOI circuit is composed of single-device islands, dielectrically isolated from each other and from the underlying substrate. The lateral isolation offers more compact design and simplified technology than in bulk-Si: there is no need of wells or inter device trenches. In addition, the vertical isolation eliminates the latch-up mechanisms that are very detrimental in bulk-Si.

An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

Abstract: In this paper, we report an experimental investigation of electron mobility in ultrathin SOI MOSFETs operated in double-gate mode. Mobility is measured for silicon thickness down to approximately 5 nm and for different temperatures. Mobility data in single- and double-gate mode are then compared according to two different criteria imposing either the same total inversion charge density or the same effective field in the two operating modes. Our results demonstrate that for silicon films around 10 nm or thinner and at small inversion densities, a modest but unambiguous mobility improvement for double-gate mode operation is observed even if the same effective field as in the single-gate mode is kept. Furthermore, we also document that the mobility in double-gate mode can improve markedly above single-gate mobility when the comparison is made at the same total inversion density. This latter feature of the double-gate operating mode can be very beneficial in the perspective of very-low voltage operation.

Process for ultra-thin body soi devices that incorporate epi silicon tips and article made thereby

Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

Seventy-fold enhancement of light extraction from a defectless photonic crystal made on silicon-on-insulator

Abstract: Very high photoluminescence extraction is observed from defectless two-dimensional photonic crystals etched in the upper 200-nm-thick silicon layer of a silicon-on-insulator (SOI) substrate. Predicted very low group velocity modes near the Γ point of the band structure lying above the light line are used to extract light from the photonic crystal slab into the free space. It is found that light is extracted on a 80-nm-wide band along directions near to the perpendicular to the slab, with an extraction enhancement up to 70 compared to an unpatterned SOI.