Showing papers on "Silicon on insulator published in 2006"

The Past, Present, and Future of Silicon Photonics

Abstract: The pace of the development of silicon photonics has quickened since 2004 due to investment by industry and government. Commercial state-of-the-art CMOS silicon-on-insulator (SOI) foundries are now being utilized in a crucial test of 1.55-mum monolithic optoelectronic (OE) integration, a test sponsored by the Defense Advanced Research Projects Agency (DARPA). The preliminary results indicate that the silicon photonics are truly CMOS compatible. RD however, lasing has not yet been attained. The new paradigm for the Si-based photonic and optoelectric integrated circuits is that these chip-scale networks, when suitably designed, will operate at a wavelength anywhere within the broad spectral range of 1.2-100 mum, with cryocooling needed in some cases

Silicon photonics

Abstract: The silicon chip has been the mainstay of the electronics industry for the last 40 years and has revolutionized the way the world operates. Today, a silicon chip the size of a fingernail contains nearly 1 billion transistors and has the computing power that only a decade ago would take up an entire room of servers. As the relentless pursuit of Moore's law continues, and Internet-based communication continues to grow, the bandwidth demands needed to feed these devices will continue to increase and push the limits of copper-based signaling technologies. These signaling limitations will necessitate optical-based solutions. However, any optical solution must be based on low-cost technologies if it is to be applied to the mass market. Silicon photonics, mainly based on SOI technology, has recently attracted a great deal of attention. Recent advances and breakthroughs in silicon photonic device performance have shown that silicon can be considered a material onto which one can build optical devices. While significant efforts are needed to improve device performance and commercialize these technologies, progress is moving at a rapid rate. More research in the area of integration, both photonic and electronic, is needed. The future is looking bright. Silicon photonics could provide low-cost opto-electronic solutions for applications ranging from telecommunications down to chip-to-chip interconnects, as well as emerging areas such as optical sensing technology and biomedical applications. The ability to utilize existing CMOS infrastructure and manufacture these silicon photonic devices in the same facilities that today produce electronics could enable low-cost optical devices, and in the future, revolutionize optical communications

Strained silicon as a new electro-optic material

Abstract: For decades, silicon has been the material of choice for mass fabrication of electronics. This is in contrast to photonics, where passive optical components in silicon have only recently been realized. The slow progress within silicon optoelectronics, where electronic and optical functionalities can be integrated into monolithic components based on the versatile silicon platform, is due to the limited active optical properties of silicon. Recently, however, a continuous-wave Raman silicon laser was demonstrated; if an effective modulator could also be realized in silicon, data processing and transmission could potentially be performed by all-silicon electronic and optical components. Here we have discovered that a significant linear electro-optic effect is induced in silicon by breaking the crystal symmetry. The symmetry is broken by depositing a straining layer on top of a silicon waveguide, and the induced nonlinear coefficient, chi(2) approximately 15 pm V(-1), makes it possible to realize a silicon electro-optic modulator. The strain-induced linear electro-optic effect may be used to remove a bottleneck in modern computers by replacing the electronic bus with a much faster optical alternative.

Silicon CMOS devices beyond scaling

Abstract: To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

Compact Wavelength-Selective Functions in Silicon-on-Insulator Photonic Wires

Abstract: We present a number of compact wavelength-selective elements implemented in silicon-on-insulator (SOI) photonic wires. These include arrayed waveguide gratings (AWGs), Mach-Zehnder lattice filters (MZLFs), and ring resonators. The circuits were fabricated with deep UV lithography. We also address the sensitivity of photonic wires to phase noise by selectively broadening the waveguides, and demonstrate this in a compact AWG with -20 dB crosstalk and an insertion loss of 2.2 dB for the center channels

High efficiency Silicon-on-Insulator grating coupler based on a poly-Silicon overlay

Abstract: A high efficiency broadband grating coupler for Silicon-On-Insulator waveguides was designed. The grating coupler is defined by locally adding a poly-Silicon layer on top of the existing waveguide layer structure prior to grating etching. Adding this poly-Silicon layer reshapes the grating structure which changes its diffraction properties. Coupling efficiencies as high as 78% at a wavelength of 1.55 mum are calculated and the optical 3dB bandwidth of the device is about 85 nm. The device layout is compatible with standard CMOS technology processing.

A Silicon-on-Insulator Photonic Wire Based Evanescent Field Sensor

Abstract: We demonstrate a new, highly sensitive evanescent field sensor using silicon-on-insulator (SOI) photonic wire waveguides Theoretical analysis shows that thin SOI waveguides can provide higher sensitivity over devices based in all other common planar waveguide material systems for the probing of both thin adsorbed biomolecular layers and bulk homogeneous solutions A Si photonic wire waveguide was incorporated into a Mach-Zehnder interferometer based sensor, configured to monitor the index change of a homogeneous solution High effective index change of 031 per refractive index unit (RIU) change of the solution was measured, confirming theoretical predictions

Transport spectroscopy of a single dopant in a gated silicon nanowire.

Abstract: We report on spectroscopy of a single dopant atom in silicon by resonant tunneling between source and drain of a gated nanowire etched from silicon on insulator. The electronic states of this dopant isolated in the channel appear as resonances in the low temperature conductance at energies below the conduction band edge. We observe the two possible charge states successively occupied by spin-up and spin-down electrons under magnetic field. The first resonance is consistent with the binding energy of the neutral D0 state of an arsenic donor. The second resonance shows a reduced charging energy due to the electrostatic coupling of the charged D? state with electrodes. Excited states and Zeeman splitting under magnetic field present large energies potentially useful to build atomic scale devices.

Laser emission and photodetection in an InP/InGaAsP layer integrated on and coupled to a Silicon-on-Insulator waveguide circuit.

Abstract: Laser emission from an InP/InGaAsP thin film epitaxial layer bonded to a Silicon-on-Insulator waveguide circuit was observed. Adhesive bonding using divinyl-tetramethyldisiloxane-benzocyclobutene (DVS-BCB) was used to integrate the InP/InGaAsP epitaxial layers onto the waveguide circuit. Light is coupled from the laser diode into an underlying waveguide using an adiabatic inverted taper approach. 0.9mW optical power was coupled into the SOI waveguide using a 500mum long laser. Besides for use as a laser diode, the same type of devices can be used as a photodetector. 50mum long devices obtained a responsivity of 0.23A/W.

Integrated circuit and method for its manufacture

Abstract: An integrated circuit and methods for its manufacture are provided. The integrated circuit (20) comprises a bulk silicon substrate (24) having a first region (64, 66) of (100) crystalline orientation and a second region (66, 64) of (110) crystalline orientation. A layer (62) of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor (96, 98) is formed in the layer (62) of silicon on insulator, at least one P-channel field effect transistor (90, 92) is formed in the second region (66, 64) of (110) crystalline orientation, and at least one N-channel field effect transistor (90, 92) is formed in the first region (64, 66) of (100) crystalline orientation.

A Fully Integrated 4 $\times$ 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 $\mu{\hbox {m}}$ CMOS SOI Technology

Abstract: A dual-channel 10 Gb/s per channel single-chip optoelectronic transceiver has been demonstrated in a 0.13-mum CMOS SOI technology. The transceiver integrates conventionally discrete optoelectronic functions such as high-speed 10-Gb/s electro-optic modulation and 10-Gb/s optical reception on an SOI substrate using a standard CMOS process. The high optical index contrast between silicon (n=3.5) and its oxide (n=1.5) allows for very large scale integration of optical devices, while the use of a standard CMOS process allows these devices to be seamlessly fabricated together with electronics on the same substrate. Such a high level of optoelectronic integration is unprecedented, and serves to substantially reduce system footprint and power dissipation, allowing efficient scaling to higher data rates and broader functionality. This paper describes the photonic components, electronic blocks, and architecture of a CMOS photonic transceiver that achieves an aggregate data rate of 20Gb/s in a dual-channel package, with a BER of less than 10-15 and a power consumption of 1.25 W per channel with both channels operating simultaneously

High-speed mechanically flexible single-crystal silicon thin-film transistors on plastic substrates

Abstract: This letter describes the fabrication and properties of bendable single-crystal-silicon thin film transistors formed on plastic substrates. These devices use ultrathin single-crystal silicon ribbons for the semiconductor, with optimized device layouts and low-temperature gate dielectrics. The level of performance that can be achieved approaches that of traditional silicon transistors on rigid bulk wafers: effective mobilities>500cm/sup 2//V/spl middot/s, ON/OFF ratios >10/sup 5/, and response frequencies > 500 MHz at channel lengths of 2 /spl mu/m. This type of device might provide a promising route to flexible digital circuits for classes of applications whose performance requirements cannot be satisfied with organic semiconductors, amorphous silicon, or other related approaches.

Thermal annealing in hydrogen for 3-D profile transformation on silicon-on-insulator and sidewall roughness reduction

Abstract: A fast, effective process using hydrogen annealing is introduced to perform profile transformation on silicon-on-insulator (SOI) and to reduce sidewall roughness on silicon surfaces. By controlling the dimensions of as-etched structures, microspheres with 1 /spl mu/m radii, submicron wires with 0.5 /spl mu/m radii, and a microdisk toroid with 0.2 /spl mu/m toroidal radius have been successfully demonstrated on SOI substrates. Utilizing this technique, we also observe the root-mean-square (rms) sidewall roughness dramatically reduced from 20 to 0.26 nm. A theoretical model is presented to analyze the profile transformation, and experimental results show this process can be engineered by several parameters including temperature, pressure, and time.

Electronic transport in nanometre-scale silicon-on-insulator membranes

Abstract: The widely used ‘silicon-on-insulator’ (SOI) system consists of a layer of single-crystalline silicon supported on a silicon dioxide substrate. When this silicon layer (the template layer) is very thin, the assumption that an effectively infinite number of atoms contributes to its physical properties no longer applies, and new electronic, mechanical and thermodynamic phenomena arise1,2,3,4, distinct from those of bulk silicon. The development of unusual electronic properties with decreasing layer thickness is particularly important for silicon microelectronic devices, in which (001)-oriented SOI is often used5,6,7. Here we show—using scanning tunnelling microscopy, electronic transport measurements, and theory—that electronic conduction in thin SOI(001) is determined not by bulk dopants but by the interaction of surface or interface electronic energy levels with the ‘bulk’ band structure of the thin silicon template layer. This interaction enables high-mobility carrier conduction in nanometre-scale SOI; conduction in even the thinnest membranes or layers of Si(001) is therefore possible, independent of any considerations of bulk doping, provided that the proper surface or interface states are available to enable the thermal excitation of ‘bulk’ carriers in the silicon layer.

Ring oscillators for CMOS process tuning and variability control

Abstract: Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator (PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

Abstract: System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 mum) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16times increase over standard chip I/O, a 20times to 100times increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single "virtual chip."

Mode conversion losses in silicon-on-insulator photonic wire based racetrack resonators

Abstract: Two complimentary types of SOI photonic wire based devices, the add/drop (A/D) filter using a racetrack resonator and the Mach-Zehnder interferometer with one arm consisting of an identical resonator in all-pass filter (APF) configuration, were fabricated and characterized in order to extract the optical properties of the resonators and predict the performance of the optical delay lines based on such resonators. We found that instead of well-known waveguide bending and propagation losses, mode conversion loss in the coupling region of such resonators dominates when the air gap between the racetrack resonator and access waveguide is smaller than 120nm. We also show that this additional loss significantly degrades the performance of the optical delay line containing cascaded resonators in APF configuration.

High-speed strained-single-crystal-silicon thin-film transistors on flexible polymers

Abstract: We fabricate thin-film transistors (TFTs) on both strained and unstrained single-crystal Si membranes transferred to flexible-polymer substrates. The active layer is transferred from the starting silicon on insulator (SOI) using a simple, fast, and reliable dry-printing method. When a multilayer Si∕SiGe∕Si structure is pseudomorphically grown on SOI and the buried oxide is selectively removed, strained Si with a negligible density of dislocations is achieved via elastic strain sharing between the SiGe alloy layer and the Si layers. Both the drain current and the transconductance of TFTs fabricated on this strained Si∕SiGe∕Si membrane after its transfer to the flexible polymer are much higher than of TFTs fabricated on the unstrained-Si counterpart.

All-optical efficient wavelength conversion using silicon photonic wire waveguide

Abstract: We demonstrate efficient wavelength conversion using a four-wave-mixing (FWM) effect in a silicon photonic wire waveguide with spot size converters. Applying a continuously operated 160-mW pump, power density in the waveguide's core was increased up to around 430 MW/cm/sup 2/, and the FWM effect was remarkably enhanced. Internal conversion efficiency obtained in an experiment was -10.6 dB. The efficiency was significantly limited by the free-carrier absorption effect.

Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs

Abstract: The statistical transient response of floating body SOI and bulk devices is measured under proton and heavy ion irradiation. The influence of the device architecture is analyzed in detail for several generations of technologies, from 0.25 mum to 70nm. The effects of the measured transients on SET sensitivity are investigated. The amount of collected charge and the shape of the transient currents are shown to have a significant impact on the temporal width of propagating transients. Finally, based on our measured data, the threshold LET and the critical transient width for unattenuated propagation are calculated for both bulk and floating body SOI as a function of technology scaling. We show that the threshold LETs and the critical transient widths for bulk and floating body SOI devices are similar. Body ties can be used to harden SOI ICs to digital SET. However, the primary advantage of SOI technologies, even with a floating body design, mostly lies in shorter transients, at a given ion LET, for SOI technologies than for bulk technologies

Compact wavelength router based on a Silicon-on-insulator arrayed waveguide grating pigtailed to a fiber array.

Abstract: We demonstrate a compact, fiber-pigtailed, 4-by-4 wavelength router in Silicon-on-insulator photonic wires, fabricated using CMOS processing methods. The core is an AWG with a 250GHz channel spacing and 1THz free spectral range, on a 425×155 μm2 footprint. The insertion loss of the AWG was reduced to 3.5dB by applying a two-step processing technique. The crosstalk is -12dB. The device was pigtailed using vertical fiber couplers and an eight-fiber array connector.

Development of CMOS-Compatible Integrated Silicon Photonics Devices

Abstract: This paper surveys technical challenges involved in designing and manufacturing integrated optoelectronic devices in a high-volume complementary metal-oxide-semiconductor (CMOS) microelectronic fabrication facility. The paper begins by introducing the motivations for building these devices in silicon. We discuss the advantages and challenges of both hybrid and monolithic strategies for optoelectronic integration. We then discuss the issues involved in building the devices in a standard CMOS facility, including specific technical examples. These include low-loss waveguides (WGs) for Raman lasers, fast silicon modulators, SiGe heterostructures for infrared photodetection, silicon-oxynitride (SiON) devices on silicon-on-insulator (SOI), silicon optical bench (SiOB) technology, and waveguide tapers. We conclude with a discussion and recommendations for future work in silicon photonics

Micromachined microphone and multisensor and method for producing same

Abstract: A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide layer, forming the structures, and then removing a portion of the oxide underlying the structures from a back side of the top silicon layer through trenches formed through the top silicon layer. The trenches allow sound waves to reach the diaphragm from the back side of the top silicon layer. In an SOI wafer, a cavity is formed through a bottom silicon layer and an intermediate oxide layer to expose the trenches for both removing the oxide and allowing the sound waves to reach the diaphragm. An inertial sensor may be formed on the same wafer, with various inertial sensor structures formed at substantially the same time and using substantially the same processes as corresponding microphone structures.

Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate

Abstract: The monolithic integration of germanium-on-insulator (GeOI) p-MOSFETs with silicon n-MOSFETs on a silicon substrate is demonstrated. The GeOI p-MOSFETs are fabricated on the oxide for silicon device isolation based on the newly developed rapid-melt-growth method. CMOS inverters consisting of the silicon n-MOSFET and GeOI p-MOSFET were obtained, and the measured results show that the processing of high-performance GeOI devices is compatible with bulk-silicon technology

A continuous-wave hybrid AlGaInAs-silicon evanescent laser

Abstract: We report a novel laser architecture, the hybrid silicon evanescent laser (SEL), that utilizes offset AlGaInAs quantum wells (QWs) bonded to a silicon waveguide. The silicon waveguide is fabricated on a silicon-on-insulator wafer using a complimentary metal-oxide-semiconductor-compatible process, and is subsequently bonded with the AlGaInAs QW structure using low temperature O2 plasma-assisted wafer bonding. The optical mode in the SEL is predominantly confined in the passive silicon waveguide and evanescently couples into the III-V active region providing optical gain. The SEL lases continuous wave (CW) at 1568 nm with a threshold of 23 mW. The maximum temperature for CW operation is 60degC. The maximum single-sided fiber-coupled CW output power at room temperature is 4.5 mW

Dispersion tailoring and soliton propagation in silicon waveguides

Abstract: The dispersive properties of silicon-on-insulator (SOI) waveguides are studied by using the effective-index method. Extensive calculations indicate that an SOI waveguide can be designed to have its zero-dispersion wavelength near 1.5 microm with reasonable device dimensions. Numerical simulations show that soliton-like pulse propagation is achievable in such a waveguide in the spectral region at approximately 1.55 microm. The concept of path-averaged solitons is used to minimize the impact of linear loss and two-photon absorption.

Optical interconnects : the silicon approach

Abstract: Advanced Conventional Interconnects: State of the Art, Future Trends, and Limitations.- Optical Gain in Silicon and the Quest for a Silicon Injection Laser.- Silicon Raman Laser, Amplifier, and Wavelength Converter.- Electro-Optical Modulators in Silicon.- Silicon Photodetectors and Receivers.- Active SiGe Devices for Optical Interconnects.- An Introduction to Silicon Photonics.- Submicron Silicon Strip Waveguides.- Photonic Crystal Microcircuit Elements.- On Chip Optical Waveguide Interconnect: the Problem of the In/Out Coupling.- Si Microphotonics for Optical Interconnection.- Silicon-Integrated Optics.- Free-Space Optical Interconnects.

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Abstract: Experimental results of p-channel silicon vertical tunnel field-effect transistors down to sub-50 nm channel length are shown. As predicted by two-dimensional simulations, we show that the device on-current is nearly independent of channel length scaling. As the drain current is determined by electrons tunneling from the valence band to the conduction band, we show that mobility does not play any role in determining the device characteristics. Low temperature measurements reveal weak positive temperature coefficient in the transfer characteristics due to the dependence of bandgap on temperature. However, as expected for the silicon devices, low on-current is observed. Thus, we propose a lateral tunnel FET on SiGe-on-insulator with high on-currents and symmetric performance in n-channel as well as p-channel operating modes.

Modeling and Data for Thermal Conductivity of Ultrathin Single-Crystal SOI Layers at High Temperature

Abstract: Simulations of the temperature field in silicon-on-insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This paper develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers and presents the experimental data for 50-nm-thick single-crystal silicon layers at high temperatures. The model applies to the temperature range of 300-1000 K for silicon layer thicknesses from 10 nm to 1 mum (and even bulk), which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration

Coupled resonator optical waveguides based on silicon-on-insulator photonic wires

Abstract: Coupled resonator optical waveguides (CROWs) comprised of up to 16 racetrack resonators based on silicon-on-insulator (SOI) photonic wires were fabricated and characterized. The optical properties of the CROWs were simulated using measured single resonator parameters based on a matrix approach. The group delay property of CROWs was also analyzed. The SOI based CROWs consisting of multiple resonators have extremely small footprints and can find applications in optical filtering, dispersion compensation, and optical buffering. Moreover, such CROW structure is a promising candidate for exploration of low light level nonlinear optics due to its resonant nature and compact mode size (∼0.1μm2) in photonic wire.