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Showing papers on "Silicon on insulator published in 2007"


Journal ArticleDOI
TL;DR: This work proposes a label-free biosensor based on microring cavities in Silicon-on-Insulator (SOI) that fits in an area below 10x10mum(2), and uses the avidin/biotin high affinity couple to demonstrate good repeatability and detection of protein concentrations down to 10ng/ml.
Abstract: Label-free biosensors attempt to overcome the stability and reliability problems of biosensors relying on the detection of labeled molecules We propose a label-free biosensor based on microring cavities in Silicon-on-Insulator (SOI) that fits in an area below 10x10mum(2) The resonance wavelength shift that occurs when the surroundings of a cavity is changed, is used for sensing While theoretically the performance for bulk refractive index changes is moderate (10(-5)), this device performs outstanding in terms of absolute molecular mass sensing (theoretical sensitivity of 1fg molecular mass) thanks to its extremely small dimensions We use the avidin/biotin high affinity couple to demonstrate good repeatability and detection of protein concentrations down to 10ng/ml Fabrication with Deep UV lithography allows for cheap mass production and integration with electronic functions for complete lab-on-chip devices

809 citations


Journal ArticleDOI
TL;DR: Elect electrically injected continuous-wave lasing in InP-based microdisk lasers coupled to a sub-micron silicon wire waveguide, fabricated through heterogeneous integration of InP on silicon-on-insulator (SOI).
Abstract: A compact, electrically driven light source integrated on silicon is a key component for large-scale integration of electronic and photonic integrated circuits. Here we demonstrate electrically injected continuous-wave lasing in InP-based microdisk lasers coupled to a sub-micron silicon wire waveguide, fabricated through heterogeneous integration of InP on silicon-on-insulator (SOI). The InP-based microdisk has a diameter of 7.5 mum and a thickness of 1 mum. A tunnel junction was incorporated to efficiently contact the p-side of the pn-junction. The laser emits at 1.6 mum, with a threshold current as low as 0.5 mA under continuous-wave operation at room temperature, and a threshold voltage of 1.65 V. The SOI-coupled laser slope efficiency was estimated to be 30 muW/mA, with a maximum unidirectional output power of 10 muW.

524 citations


Journal ArticleDOI
TL;DR: In this article, a high-speed silicon optical modulator based on the free carrier plasma dispersion effect is presented, which is based on carrier depletion of a pn diode embedded inside a silicon-on-insulator waveguide.
Abstract: A high-speed silicon optical modulator based on the free carrier plasma dispersion effect is presented. It is based on carrier depletion of a pn diode embedded inside a silicon-on-insulator waveguide. To achieve high-speed performance, a travelling-wave design is used to allow co-propagation of the electrical and optical signals along the length of the device. The resulting modulator has a 3 dB bandwidth of ~30 GHz and can transmit data up to 40 Gbit/s.

428 citations


Journal ArticleDOI
Tao Yin1, Rami Cohen1, Mike Morse1, Gadi Sarid1, Yoel Chetrit1, Doron Rubin1, Mario J. Paniccia1 
TL;DR: Evanescently coupled Ge waveguide photodetectors that are grown on top of Si rib waveguides that have an optical bandwidth of 31.3 GHz at -2V for 1550nm are reported on.
Abstract: We report on evanescently coupled Ge waveguide photodetectors that are grown on top of Si rib waveguides. A Ge waveguide detector with a width of 7.4mum and length of 50 mum demonstrated an optical bandwidth of 31.3 GHz at -2V for 1550nm. In addition, a responsivity of 0.89 A/W at 1550 nm and dark current of 169 nA were measured from this detector at -2V. A higher responsivity of 1.16 A/W was also measured from a longer Ge waveguide detector (4.4 x 100 mum2), with a corresponding bandwidth of 29.4 GHz at -2V. An open eye diagram at 40 Gb/s is also shown.

401 citations


Journal ArticleDOI
TL;DR: Values up to gamma=7 x 10(6)/(W km) for the nonlinear parameter are feasible if silicon-on-insulator based strip and slot waveguides are properly designed, and this enables ultrafast all-optical signal processing with nonresonant compact devices.
Abstract: Values up to gamma=7 x 10(6)/(W km) for the nonlinear parameter are feasible if silicon-on-insulator based strip and slot waveguides are properly designed This is more than three orders of magnitude larger than for state-of-the-art highly nonlinear fibers, and it enables ultrafast all-optical signal processing with nonresonant compact devices At lambda=155 microm we provide universal design curves for strip and slot waveguides which are covered with different linear and nonlinear materials, and we calculate the resulting maximum gamma

395 citations


Journal ArticleDOI
TL;DR: A compact crossings for silicon-on-insulator photonic wires is presented using a 3 microm parabolic taper in each arm and locally applying a lower index contrast using a double-etch technique to reduce loss of confinement.
Abstract: We present compact crossings for silicon-on-insulator photonic wires. The waveguides are broadened using a 3μm parabolic taper in each arm. By locally applying a lower index contrast using a double-etch technique, loss of confinement is reduced and 97.5% transmission (−1.7dB) is achieved with only −40dB cross talk.

337 citations


Journal ArticleDOI
TL;DR: In this paper, an eight-fold length reduction of the coupling structure from fiber to photonic wire in SOI, as compared to a linear grating and adiabatic taper, is obtained, without performance penalty.
Abstract: We report experimental results on compact and broadband focusing grating couplers, both in silicon-on-insulator (SOI) and gold on SOI. An eight-fold length reduction of the coupling structure from fiber to photonic wire in SOI, as compared to a linear grating and adiabatic taper, is obtained, without performance penalty. A proof of principle is given for a focusing grating coupler in gold on SOI, with 20% fiber-to-focus efficiency.

289 citations


Journal ArticleDOI
TL;DR: It is found that nanowires of width >150 nm are virtually insensitive to the buffer pH, and computer simulations confirm this behavior and show that sensing can be extended even down to the single charge level.
Abstract: Silicon nanowires of different widths were fabricated in silicon on insulator (SOI) material using conventional process technology combined with electron-beam lithography. The aim was to analyze th ...

266 citations


Journal ArticleDOI
TL;DR: In this paper, the authors describe the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, p-gate and gate-all-around) structures.

246 citations


Journal ArticleDOI
TL;DR: This is the first demonstration of a functional polarization-diversity circuit implemented in SOI nanophotonic waveguides, including interfaces to single-mode fiber, and it is shown that polarization insensitive operation is achieved through a special polarization diversity approach.
Abstract: We present a wavelength duplexer based on a compact arrayed waveguide grating (AWG) in silicon-on-insulator photonic wire waveguides. Polarization insensitive operation is achieved through a special polarization diversity approach in which we use 2-D grating fiber couplers as integrated polarization splitters. To mitigate the effects of process variations, we propagated both polarizations in opposite directions through the same AWG with a mere 600x350microm(2) footprint. This resulted in an on-chip insertion loss between -2.1dB and -6.9dB, crosstalk of -15dB, and only 0.66dB polarization dependent loss. This is the first demonstration of a functional polarization-diversity circuit implemented in SOI nanophotonic waveguides, including interfaces to single-mode fiber.

245 citations


Journal ArticleDOI
TL;DR: While substrate leakage loss has warranted the necessity of substrate undercut structures in the past, it is shown here that the substrate has a very useful role to play for both passive chip-scale device integration as well as active electronic device integration.
Abstract: We report the fabrication and experimental characterization of an ultra-high Q microdisk resonator in a silicon-on-insulator (SOI) platform. We examine the role of the substrate in the performance of such microdisk resonators. While substrate leakage loss has warranted the necessity of substrate undercut structures in the past, we show here that the substrate has a very useful role to play for both passive chip-scale device integration as well as active electronic device integration. Two device architectures for the disk-on-substrate are studied in order to assess the possibility of such an integration of high Q resonators and active components. Using an optimized process for fabrication of such a resonator device, we experimentally demonstrate a Q~3×106, corresponding to a propagation loss ~0.16 dB/cm. This, to our knowledge, is the maximum Q observed for silicon microdisk cavities of this size for disk-on-substrate structures. Critical coupling for a resonance mode with an unloaded Q~0.7×106 is observed. We also report a detailed comparison of the obtained experimental resonance spectrum with the theoretical and simulation analysis. The issue of waveguide-cavity coupling is investigated in detail and the conditions necessary for the existence or lack of critical coupling is elaborated.

Journal ArticleDOI
TL;DR: In this paper, the wavelength dependence of two-photon absorption and the Kerr nonlinearity in silicon over a spectral range extending from 1.2 to 2.4μm were analyzed.
Abstract: The authors present the detailed characterization of the wavelength dependence of two-photon absorption and the Kerr nonlinearity in silicon over a spectral range extending from 1.2to2.4μm. They show that silicon exhibits a significant increase in its nonlinear figure of merit with increasing wavelengths beyond the two telecommunication bands. They expect their results to provide guidance for extending nonlinear silicon photonics into new spectral regimes.

Journal ArticleDOI
TL;DR: Design, fabrication and characterization of germanium on silicon photodetector integrated in SOI waveguide are reported, and a responsivity of 1 A/W and a -3 dB bandwidth of 25 GHz under 6 V bias have been obtained.
Abstract: We report the experimental demonstration of a germanium metal-semiconductor-metal (MSM) photodetector integrated in a SOI rib waveguide. Femtosecond pulse and frequency experiments have been used to characterize such photodetectors. The measured bandwidth under 6V bias is about 25 GHz at 1.55 µm wavelength with a responsivity as high as 1 A/W. The used technological processes are compatible with complementary-metal-oxide-semiconductor (CMOS) technology.

Journal ArticleDOI
TL;DR: In this article, the integration of a direct bandgap III-V epitaxial layer on top of the SOI waveguide layer by means of a die-to-wafer bonding process is presented.

Proceedings ArticleDOI
01 Dec 2007
TL;DR: In this article, the authors report record RF performance in 45-nm silicon-on-insulator (SOI) CMOS technology and demonstrate that RF performance scaling with channel length and layout optimization is demonstrated.
Abstract: We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fT's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

Patent
29 Mar 2007
TL;DR: In this paper, the authors proposed an SOI-wafer manufacturing method whereby a high-quality epitaxial layer can be grown on an SoI layer more surely than in conventional cases.
Abstract: PROBLEM TO BE SOLVED: To provide an SOI-wafer manufacturing method whereby a high-quality epitaxial layer can be grown on an SOI layer more surely than in conventional cases. SOLUTION: The SOI-wafer manufacturing method is the one wherein an SOI layer and an epitaxial layer are formed on an insulator by at least creating a substrate whereon the SOI layer is formed on the insulator, and by growing the epitaxial layer on the SOI layer. After at least creating the substrate wherein the SOI layer is formed on the insulator, and before growing the epitaxial layer, the substrate is subjected to an HF processing. Thereafter, the epitaxial layer is grown on the SOI layer. COPYRIGHT: (C)2008,JPO&INPIT

Journal ArticleDOI
Kenneth P. Rodbell1, David F. Heidel1, H.H.K. Tang1, M.S. Gordon1, Phil Oldiges1, Conal E. Murray1 
TL;DR: In this article, experimental data showed that low energy (<2 MeV) proton irradiation can upset exploratory 65 nm node, silicon-on-insulator circuits and suggested that track structures need to be understood and effectively modeled, especially for small, modern devices.
Abstract: Experimental data are presented showing that low energy (<2 MeV) proton irradiation can upset exploratory 65 nm node, silicon-on-insulator circuits. Alpha particle SER data, modeling and simulation results provide a plausible mechanism. This work suggests that track structures need to be understood and effectively modeled, especially for small, modern devices.

Journal ArticleDOI
TL;DR: In this paper, a planar concave grating (PCG) demultiplexer was fabricated on a nanophotonic SOI platform using standard wafer scale CMOS processes including deep-UV lithography.
Abstract: We show that a nanophotonic silicon-on-insulator (SOI) platform offers many advantages for the implementation of planar concave grating (PCG) demultiplexers, as compared with other material systems. We present for the first time the design and measurement results of a PCG demultiplexer fabricated on a nanophotonic SOI platform using standard wafer scale CMOS processes including deep-UV lithography. Our PCG device has four wavelength channels with a channel spacing of 20 nm and a record-small footprint of 280times150 mum. The on-chip loss is 7.5 dB, and the crosstalk is better than -30 dB

Journal ArticleDOI
Abstract: Composite micromechanical resonators were encapsulated in a hermetic environment using a wafer-scale encapsulation process compatible with complementary metal-oxide semiconductor processing. The resonator structure is comprised of single crystal silicon with a silicon dioxide coating and shows a frequency-temperature sensitivity that is comparable to uncompensated quartz crystal resonators. A frequency variation of less than 200ppm is achieved over a −40–125°C temperature range. The resonator exhibits a quadratic temperature behavior with a turnover temperature at which the frequency becomes insensitive to small temperature changes. The turnover temperature can be controlled for use in high precision frequency references.

Journal ArticleDOI
TL;DR: In this paper, a micron-size electro-optic modulator using a high-index-contrast silicon Fabry-Perot resonator cavity was demonstrated at speeds of 250 Mbps limited only by fabrication imperfections.
Abstract: We experimentally demonstrate a micron-size electro-optic modulator using a high-index-contrast silicon Fabry-Perot resonator cavity. This compact device consists of a 1-D cavity formed within a single mode silicon channel waveguide and an embedded p-i-n junction on a silicon-oninsulator platform. The entire device is 6.0 microns in length. We demonstrate modulation depths as large as 5.87 dB at speeds of 250 Mbps limited only by fabrication imperfections, with optimized theoretical speeds of several Gbps.

Journal ArticleDOI
TL;DR: Compact silicon-on-insulator waveguide thermo-optically tunable Fabry-Perot microcavities with silicon/air Bragg mirrors with high-Q cavities enabling fast switching at low drive power (<10 mW) are demonstrated.
Abstract: Compact silicon-on-insulator (SOI) waveguide thermo-optically tunable Fabry-Perot microcavities with silicon/air Bragg mirrors are demonstrated. Quality factors of Q=4,584 are measured with finesse F=82. Tuning is achieved by flowing current directly through the silicon cavity resulting in efficient thermo-optic tuning over 2 nm for less than 50 mW applied electrical power. The high-Q cavities enable fast switching (1.9 μs rise time) at low drive power (<10 mW). By overdriving the device, rise times of 640 ns are obtained. Various device improvements are discussed.

Journal ArticleDOI
TL;DR: In this paper, the authors reported the first experimental observation in the optical domain of a dramatic width-dependent lateral leakage loss behavior for the TM-like mode of tight vertical confinement ridge waveguides formed in silicon-on-insulator.
Abstract: We report the first experimental observation in the optical domain of a dramatic width-dependent lateral leakage loss behavior for the TM-like mode of tight vertical confinement ridge waveguides formed in silicon-on-insulator. The lateral leakage loss displays a series of sharp cyclic minima at precise waveguide widths, and appears to be inherent to waveguide geometries of central importance to a wide variety of active devices in silicon photonics requiring lateral electrical access. This behavior is not predicted by the often-used effective-index-based methods, but is understood phenomenologically and also compared to prior numerical analysis and predictions of leaky mode behavior. It is shown that TM-like mode operation, critical to the operation of some active component designs, will require precision control of waveguide dimensions to achieve high performance

Journal ArticleDOI
TL;DR: Pretet et al. as discussed by the authors investigated the super-coupling effect in fully depleted SOI devices and revealed new challenges in the characterization of ultra-thin devices, such as gate oxide tunneling, thin buried oxide, and ultra thin films.
Abstract: A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed simulations and analytical modelling of the potential and electron/hole concentrations. The enhancement of the interface coupling effect in ultra thin body devices, called super-coupling, can explain previously published experimental data [Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87], and reveals new challenges in the characterization of advanced SOI devices.

Journal ArticleDOI
TL;DR: A novel approach to selectively functionalize the surface of silicon nanowires located on silicon-based substrates based upon highly localized nanoscale Joule heating along silicon Nanowires under an applied electrical bias is reported.
Abstract: In this letter, we report a novel approach to selectively functionalize the surface of silicon nanowires located on silicon-based substrates. This method is based upon highly localized nanoscale Joule heating along silicon nanowires under an applied electrical bias. Numerical simulation shows that a high-temperature (>800 K) with a large thermal gradient can be achieved by applying an appropriate electrical bias across silicon nanowires. This localized heating effect can be utilized to selectively ablate a protective polymer layer from a region of the chosen silicon nanowire. The exposed surface, with proper postprocessing, becomes available for surface functionalization with chemical linker molecules, such as 3-mercaptopropyltrimethoxysilanes, while the surrounding area is still protected by the chemically inert polymer layer. This approach is successfully demonstrated on silicon nanowire arrays fabricated on SOI wafers and visualized by selective attachment of gold nanoparticles.

Journal ArticleDOI
TL;DR: A preliminary assessment of this novel intracellular sensor with electrical conductance measurement under different pH levels is demonstrated and it is expected that this sensor with proper chemical modification will enable localized biochemical sensing within biological cells, such as neurotransmitter activities during the synaptic communication between neuron cells.

Patent
19 Apr 2007
TL;DR: A 3D integrated circuit (IC), 3D IC chip and method of fabricating a 3DIC chip are discussed in this article, which includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements.
Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Journal ArticleDOI
TL;DR: In this paper, the short-channel properties of multi-gate SOI MOSFETs were analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness, and the radius of curvature of the corners.
Abstract: The short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as DIBL, subthreshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. This number ranges from 2 for a double-gate device to 4 in a gate-all-around transistor. The equivalent gate number can be used in general equations to predict the absence or presence of short-channel effects. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the temperature dependence of a silicon-on-insulator-based silicon nanophotonic ring resonator covered with a polymeric overlayer.
Abstract: In this paper, we investigate the temperature dependence of a silicon-on-insulator-based silicon nanophotonic ring resonator covered with a polymeric overlayer. Temperature-dependent wavelength shift is measured to be as low as 5 pm/degC for the TM mode in a silicon ring resonator composed of a 500 times 220 nm2 channel waveguide. We also show through simulations and experiments that the temperature dependence can be reduced for the TE mode or for both the TE and TM modes by adjusting the mode volume of a silicon nanophotonic waveguide.

Journal ArticleDOI
TL;DR: First demonstration of guiding light in vertical slot-waveguides on silicon nitride/silicon oxide material system and group index behavior evidences guiding and confinement in the low-index slot region at O-band (1260-1370nm) telecommunication wavelengths.
Abstract: We report on the first demonstration of guiding light in vertical slot-waveguides on silicon nitride/silicon oxide material system. Integrated ring resonators and Fabry-Perot cavities have been fabricated and characterized in order to determine optical features of the slot-waveguides. Group index behavior evidences guiding and confinement in the low-index slot region at O-band (1260–1370nm) telecommunication wavelengths. Propagation losses of <20 dB/cm have been measured for the transverse-electric mode of the slot-waveguides.

Journal ArticleDOI
TL;DR: In this article, a double-sided trenches on the buried oxide layer (DT SOI) is proposed and its breakdown characteristics are investigated theoretically and experimentally in LDMOS.
Abstract: A novel silicon-on-insulator (SOI) high-voltage device structure with double-sided trenches on the buried oxide layer (DT SOI) is proposed and its breakdown characteristics are investigated theoretically and experimentally in this letter. Theoretically, the charges implemented in the DTs, whose density changes with the drain voltage, increase the electric field in the buried layer and modulate the electric field in the drift region, which results in the enhancement of the breakdown voltage (BV). Experimentally, the BV of 730 V is obtained for the first time in SOI LDMOS with DT on 20-mum SOI layer and 1- mum buried oxide layer