Showing papers on "Silicon on insulator published in 2010"

Nonlinear silicon photonics

Abstract: The nonlinearities in silicon are diverse. This Review covers the wealth of nonlinear effects in silicon and highlights the important applications and technological solutions in nonlinear silicon photonics. The increasing capability for manufacturing a wide variety of optoelectronic devices from polymer and polymer–silicon hybrids, including transmission fibre, modulators, detectors and light sources, suggests that organic photonics has a promising future in communications and other applications.

III‐V/silicon photonics for on‐chip and intra‐chip optical interconnects

Abstract: In this paper III-V on silicon-on-insulator (SOI) het- erogeneous integration is reviewed for the realization of near infrared light sources on a silicon waveguide platform, suitable for inter-chip and intra-chip optical interconnects. Two bonding technologies are used to realize the III-V/SOI integration: one based on molecular wafer bonding and the other based on DVS- BCB adhesive wafer bonding. The realization of micro-disk lasers, Fabry-Perot lasers, DFB lasers, DBR lasers and mode- locked lasers on the III-V/SOI material platform is discussed. Artist impression of a multi-wavelength laser based on micro- disk cavities realized on a III-V/SOI heterogeneous platform and a microscope image of a realized structure.

Silicon-on-Insulator Spectral Filters Fabricated With CMOS Technology

Abstract: We give an overview of recent progress in passive spectral filters and demultiplexers based on silicon-on-insulator photonic wire waveguides: ring resonators, interferometers, arrayed waveguide gratings, and echelle diffraction gratings, all benefit from the high-index contrast possible with silicon photonics. We show how the current generation of devices has improved crosstalk levels, insertion loss, and uniformity due to an improved fabrication process based on 193 nm lithography.

High-efficiency fiber-to-chip grating couplers realized using an advanced CMOS-compatible Silicon-On-Insulator platform

Abstract: A new generation of Silicon-on-Insulator fiber-to-chip grating couplers which use a silicon overlay to enhance the directionality and thereby the coupling efficiency is presented. Devices are realized on a 200mm wafer in a CMOS pilot line. The fabricated fiber couplers show a coupling efficiency of −1.6dB and a 3dB bandwidth of 80nm.

Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors

Abstract: Compound semiconductor materials such as gallium arsenide and indium arsenide have outstanding electronic properties, but are costly to process and cannot, on their own, compete with silicon when it comes to low-cost fabrication. But as the relentless miniaturization of silicon electronics is reaching its limits, an alternative route of enhanced device performance is becoming more attractive: the integration of compound semiconductors within silicon. Ali Javey and colleagues now present a promising new concept to integrate ultrathin layers of single-crystal indium arsenide on silicon-based substrates with an epitaxial transfer method, a technique borrowed from large-area optoelectronics. With this technique, involving the use of an elastomeric stamp to lift off indium arsenide nanowires and transfer them to a silicon-based substrate, the authors fabricate thin film transistors with excellent device performance. A potential route to enhancing the performance of electronic devices is to integrate compound semiconductors, which have superior electronic properties, within silicon, which is cheap to process. These authors present a promising new concept to integrate ultrathin layers of single-crystal indium arsenide on silicon-based substrates with an epitaxial transfer method borrowed from large-area optoelectronics. With this technique, the authors fabricate thin-film transistors with excellent device performance. Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance1,2,3,4,5,6,7,8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied7,9,10: such devices combine the high mobility of III–V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored9,11,12,13—but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO2 substrates. As a parallel with silicon-on-insulator (SOI) technology14, we use ‘XOI’ to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO x layer (~1 nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6 mS µm−1 at a drain–source voltage of 0.5 V, with an on/off current ratio of greater than 10,000.

An ultra-small, low power all-optical flip-flop memory on a silicon chip

Abstract: Ultra-small, low-power, all-optical switching and memory elements, such as all-optical flip-flops, as well as photonic integrated circuits of many such elements, are in great demand for all-optical signal buffering, switching and processing. Silicon-on-insulator is considered to be a promising platform to accommodate such photonic circuits in large-scale configurations. Through heterogeneous integration of InP membranes onto silicon-on-insulator, a single microdisk laser with a diameter of 7.5 µm, coupled to a silicon-on-insulator wire waveguide, is demonstrated here as an all-optical flip-flop working in a continuous-wave regime with an electrical power consumption of a few milliwatts, allowing switching in 60 ps with 1.8 fJ optical energy. The total power consumption and the device size are, to the best of our knowledge, the smallest reported to date at telecom wavelengths. This is also the only electrically pumped, all-optical flip-flop on silicon built upon complementary metal-oxide semiconductor technology. Scientists demonstrate that a single 7.5-μm-diameter microdisk laser coupled to a silicon-on-insulator wire waveguide can work as an all-optical flip-flop memory. Under a continuous bias of 3.5 mA, flip-flop operation is demonstrated using optical triggering pulses of 1.8 fJ and with a switching time of 60 ps. This device is attractive for on-chip all-optical signal buffering, switching, and processing.

Subwavelength grating periodic structures in silicon-on-insulator: a new type of microphotonic waveguide.

Abstract: We report on the experimental demonstration and analysis of a new waveguide principle using subwavelength gratings. Unlike other periodic waveguides such as line-defects in a 2D photonic crystal lattice, a subwavelength grating waveguide confines the light as a conventional index-guided structure and does not exhibit optically resonant behaviour. Subwavelength grating waveguides in silicon-on-insulator are fabricated with a single etch step and allow for flexible control of the effective refractive index of the waveguide core simply by lithographic patterning. Experimental measurements indicate a propagation loss as low as 2.1 dB/cm for subwavelength grating waveguides with negligible polarization and wavelength dependent loss, which compares favourably to conventional microphotonic silicon waveguides. The measured group index is nearly constant n(g) ~1.5 over a wavelength range exceeding the telecom C-band.

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

Abstract: In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage and drain induced barrier lowering. A model for the drain current, transconductance, drain conductance and voltage gain is also discussed. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

An ultra-small, low-power all-optical flip-flop memory on a silicon chip

Abstract: A 7.5pm-diameter InP microdisk laser, integrated on an SOI waveguide is demonstrated as all-optical flip-flop working in continuous-wave regime with an electrical power consumption of several mW, and allowing switching in 60ps with pulses of 1.8fJ.

Fabrication and Characterization of the Charge-Plasma Diode

Abstract: We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.

Silicon photonics manufacturing.

Abstract: Most demonstrations in silicon photonics are done with single devices that are targeted for use in future systems. One of the costs of operating multiple devices concurrently on a chip in a system application is the power needed to properly space resonant device frequencies on a system's frequency grid. We asses this power requirement by quantifying the source and impact of process induced resonant frequency variation for microdisk resonators across individual die, entire wafers and wafer lots for separate process runs. Additionally we introduce a new technique, utilizing the Transverse Electric (TE) and Transverse Magnetic (TM) modes in microdisks, to extract thickness and width variations across wafers and dice. Through our analysis we find that a standard six inch Silicon on Insulator (SOI) 0.35 μm process controls microdisk resonant frequencies for the TE fundamental resonances to within 1 THz across a wafer and 105 GHz within a single die. Based on demonstrated thermal tuner technology, a stable manufacturing process exhibiting this level of variation can limit the resonance trimming power per resonant device to 231 μW. Taken in conjunction with the power to compensate for thermal environmental variations, the expected power requirement to compensate for fabrication-induced non-uniformities is 17% of that total. This leads to the prediction that thermal tuning efficiency is likely to have the most dominant impact on the overall power budget of silicon photonics resonator technology.

Top-down fabricated silicon nanowire sensors for real-time chemical detection

Abstract: Silicon nanowire (SiNW) sensors have been developed by using top-down fabrication that is CMOS (complementary metal‐oxide‐semiconductor) compatible for resistive chemical detection with fast response and high sensitivity. Top-down fabrication by electron beam lithography and reactive ion etching of a silicon on insulator (SOI) substrate enables compatibility with the CMOS fabrication process, accurate alignment with other electrical components, flexible design of the nanowire geometry and good control of the electrical characteristics. The SiNW sensors showed a large operation range for pH detection (pH = 4‐10) with an average sensitivity of (� R/R)/pH = 2.6%/pH and a rise time of 8 s. A small pH level difference (� pH = 0.2) near neutral pH conditions (pH = 7) could be resolved with the SiNW sensors. The sensor response to the presence of alkali metal ions and the long term drifting effects were also investigated. (Some figures in this article are in colour only in the electronic version)

High speed carrier-depletion modulators with 1.4V-cm V(pi)L integrated on 0.25microm silicon-on-insulator waveguides.

Abstract: We demonstrate a very efficient high speed silicon modulator with an ultralow pi-phase-shift voltage-length product V(pi)L = 1.4V-cm. The device is based on a Mach-Zehnder interferometer (MZI) fabricated using 0.25microm thick silicon-on-insulator (SOI) waveguide with offset lateral PN junctions. Optimal carrier-depletion induced index change has been achieved through the optimization of the overlap region of carriers and photons. The 3dB bandwidth of a typical 1mm long device was measured to be more than 12GHz. An eye-diagram taken at a transmission rate of 12.5Gb/s confirms the high speed capability of the device.

Highly efficient nonuniform grating coupler for silicon-on-insulator nanophotonic circuits

Abstract: We present design, fabrication, and characterization of a silicon-on-insulator grating coupler of high efficiency for coupling between a silicon nanophotonic waveguide and a single mode fiber. By utilizing the lag effect of the dry etching process, a grating coupler consisting of nonuniform grooves with different widths and depths is designed and fabricated to maximize the overlapping between the upward wave and the fiber mode. The measured waveguide-to-fiber coupling efficiency of 64% (-1.9 dB) for the transverse electric polarization is achieved by the present nonuniform grating coupler directly defined on a regular silicon-on-insulator wafer.

Wavelength Division Multiplexing Based Photonic Integrated Circuits on Silicon-on-Insulator Platform

Abstract: We review recent advances in the development of silicon photonic integrated circuits for high-speed and high-capacity interconnect applications. We present detailed design, fabrication, and characterization of a silicon integrated chip based on wavelength division multiplexing. In such a chip, an array of eight high-speed silicon optical modulators is monolithically integrated with a silicon-based demultiplexer and a multiplexer. We demonstrate that each optical channel operates at 25 Gb/s. Our measurements suggest the integrated chip is capable of transmitting data at an aggregate rate of 200 Gb/s. This represents a key milestone on the way for fabricating terabit per second transceiver chips to meet the demand of future terascale computing.

Methods of forming printable integrated circuit devices and devices formed thereby

Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

Roughness induced backscattering in optical silicon waveguides.

Abstract: We report on the direct observation of backscattering induced by sidewall roughness in high-index-contrast optical waveguides based on total internal reflection. Our results demonstrate that backscattering is one of the most severe limiting factors in state-of-the art silicon on insulator nanowires employed in densely integrated photonics. We also derive the general relationship between backscattering and geometrical and optical parameters of the waveguide. Further, the role of roughness in polarization rotation and coupling with higher-order modes is pointed out.

Fabrication of microdevices with integrated nanowires for investigating low-dimensional phonon transport.

Abstract: Phonons in low-dimensional structures with feature sizes on the order of the phonon wavelength may be coherently scattered by the boundary. This may give rise to a new regime of heat conduction, which can impact thermal energy transport and conversion. Traditional methods used to investigate phonon transport in one-dimensional structures suffer from uncertainty due to contact resistance, defects, and limited control over sample dimensions. We have developed a new batch-fabrication technique for suspended microdevices with integrated silicon nanowires from silicon-on-insulator (SOI) wafers. The nanowires are defect-free and have extremely high aspect ratios (length/critical dimension >2000). The nanowire dimensions (length and critical dimension) can be precisely controlled during fabrication. With these novel devices, phonon transport in silicon nanowires is systematically investigated. The room temperature thermal conductivity of nanowires with critical width around 80 nm is about 20 W/(m K) and much lower than that in smooth VLS wires. This suggests that the surface morphology of the structures has a significant effect on the thermal conductivity, but this phenomenon is not currently understood. This fabrication technique can also be used for thermal transport investigation in a wide-range of low-dimensional structures.

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs

Abstract: Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that LEFF of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.

Low-Loss ( $ 1 dB) and Polarization-Insensitive Edge Fiber Couplers Fabricated on 200-mm Silicon-on-Insulator Wafers

Abstract: We present a silicon-on-insulator (SOI) polarization-insensitive fiber-to-fiber coupler fabricated on a 200-mm wafer with the standard complementary metal-oxide-semiconductor technology. The coupling losses from a lensed fiber into a 500-nm-wide SOI waveguide were measured to be less than 1 dB in the 1520- to 1600-nm spectral range and below 3 dB between 1300 and 1600 nm.

Highly-efficient thermally-tuned resonant optical filters

Abstract: We demonstrate spectral tunability for microphotonic add-drop filters manufactured as ring resonators in a commercial 130 nm SOI CMOS technology. The filters are provisioned with integrated heaters built in CMOS for thermal tuning. Their thermal impedance has been dramatically increased by the selective removal of the SOI handler substrate under the device footprint using a bulk silicon micromachining process. An overall ~20x increase in the tuning efficiency has been demonstrated with a 100 µm radius ring as compared to a pre-micromachined device. A total of 3.9 mW of applied tuning power shifts the filter resonant peak across one free spectral node of the device. The Q-factor of the resonator remains unchanged after the co-integration process and hence this device geometry proves to be fully CMOS compatible. Additionally, after the cointegration process our result of 2π shift with 3.9mW power is among the best tuning performances for this class of devices. Finally, we examine scaling the tuning efficiency versus device footprint to develop a different performance criterion for an easier comparison to evaluate thermal tuning. Our criterion is defined as the unit of power to shift the device resonance by a full 2π phase shift.

Compact broadband polarizer based on shallowly-etched silicon-on-insulator ridge optical waveguides

Abstract: A new way to make broadband polarizers on silicon-on-insulator (SOI) waveguides is proposed, analyzed and characterized. The characteristics of the eigenmodes in a shallowly-etched SOI ridge optical waveguide are analyzed by using a full-vectorial finite-different method (FV-FDM) mode solver. The theoretical calculation shows that the loss of TE fundamental mode could be made very low while at the same time the TM fundamental mode has very large leakage loss, which is strongly dependent on the trench width. The leakage loss of the TM fundamental mode changes quasi-periodically as the trench width w(tr) varies. The formula of the period ∆w(tr) is given. By utilizing the huge polarization dependent loss of this kind of waveguide, a compact and simple optical polarizer based on a straight waveguide was demonstrated. The polarizer is fabricated on a 700 nm-thick SOI wafer and then characterized by using a free-space optical system. The measured extinction ratio is as high as 25 dB over a 100 nm wavelength range for a 1 mm-long polarizer.

Submilliwatt thermo-optic switches using free-standing silicon-on-insulator strip waveguides.

Abstract: A low power Mach-Zehnder interferometer thermo-optic switch using free-standing silicon-on-insulator strip waveguides is demonstrated. The air gap provides thermal isolation between the waveguide interferometer arms and the underlying silicon substrate. The highly confined optical modes of the strip waveguides enable miniature heated cross-sections. The heating efficiency from on-chip resistive heaters is enhanced. Measurements of fabricated devices using 100 μm arm lengths at 1550 nm wavelength result in a switching power of 540 μW, a 10% - 90% switching rise time of 141 μs, and an extinction ratio of 25 dB.

WDM multi-channel silicon photonic receiver with 320 Gbps data transmission capability

Abstract: A high performance monolithically integrated WDM receiver is fabricated on the SOI platform, with key components comprising a 1 x 32 Si-based AWG and an array of high speed waveguided Ge-on-Si photodetectors. The optical channel spacing is 200 GHz. This configuration was used to demonstrate 32-channel operation in the L-band, where it is particularly challenging for silicon photonics due to the low absorption coefficient of Ge at L-band wavelengths. Each channel is capable of operating at a data rate of at least 10 Gbps, resulting in an aggregate data rate of 320 Gbps. At a BER of 1 x 10(-11), the WDM receiver showed an optical input sensitivity between -16 dBm and -19 dBm.

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Abstract: The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its improved electrostatics and short-channel effect control. FinFETs represent one of the architectures of interest within that family together with Ω-gates, Π-gates, gate-all-around… They can readily be manufactured starting from SOI or bulk substrates even though more efforts have been dedicated to the SOI option so far. We report in this work an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations. Both alternatives show better scalability (threshold voltage – Vt vs. L) than PLANAR CMOS and exhibit similar intrinsic device performance (Ioff vs. Ion). Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced threshold voltage mismatch. Using an optimized integration to minimize parasitic capacitances and resistances we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both SOI and bulk FinFETs. SRAM cells are also reported to work, scaling similarly with the supply voltage (VDD) for the two FinFET integration schemes.

ZnO nanowires grown on SOI CMOS substrate for ethanol sensing

Abstract: This paper reports on the integration of zinc oxide nanowires (ZnO NWs) with a silicon on insulator (SOI) CMOS (complementary metal oxide semiconductor) micro-hotplate for use as an alcohol sensor. The micro-hotplates consist of a silicon resistive micro-heater embedded within a membrane (composed of silicon oxide and silicon nitride, supported on a silicon substrate) and gold bump bonded aluminum electrodes that are used to make an ohmic contact with the sensing material. ZnO NWs were grown by a simple, low-cost hydrothermal method and characterised using SEM, XRD and photoluminiscence methods. The chemical sensitivity of the on-chip NWs to ethanol vapour (at different humidity levels) was characterised at two different temperatures namely, 300 °C and 400 °C (power consumption was 24 mW and 33 mW, respectively), and the sensitivity was found to be 0.1%/ppm (response 4.7 at 4363 ppm). These results show that ZnO NWs are a promising material for use as a CMOS ethanol gas sensor that offers low cost, low power consumption and integrated circuitry.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

Abstract: We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V T -variability performances are obtained (A VT =1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V DD =0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ SNM DD =0.7V. We also demonstrate ultra-low leakage ( G = 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

High quality factor etchless silicon photonic ring resonators

Abstract: We demonstrate high-Q silicon ring resonators fabricated by selective oxidation without any silicon etching. We achieve an intrinsic quality factor of 510,000 in 50 μm-radius ring resonators with ring losses of 0.8 dB/cm.

Fabrication and application of silicon nanowire transistor arrays for biomolecular detection

Abstract: We present a novel approach for large-scale silicon nanowire (SiNW) array fabrication for bioelectronic applications. Nanoimprint lithography was combined with standard CMOS processing on 4 in. SOI wafers in order to produce highly integrated arrays of silicon nanowire field-effect transistors (SiNW-FET). With a very smooth surface due to wet anisotropic etching, SiNW-FET arrays show a good electronic performance with a subthreshold slope of about 85 mV/decade. When applying a front-gate control of the wires via an electrochemical reference electrode, reliable electronic performance inside an electrolyte solution can be achieved. Our SiNW-FET sensors exhibit almost no electronic hysteresis on forward and backward bias sweeps. In this article the fabrication process, electronic and electrochemical characterizations and first biomolecular detection experiments are presented. For biodetection experiments we used a differential readout between molecule-free wires and wires carrying covalently attached biomolecules such as short, single-stranded DNA or biotin. With our SiNW-FET arrays a reliable detection of biomolecular layers can be achieved.

SOI SiGe-base lateral bipolar junction transistor

Abstract: A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.