Showing papers on "Silicon on insulator published in 2011"

A role for graphene in silicon-based semiconductor devices

Abstract: As silicon-based electronics approach the limit of improvements to performance and capacity through dimensional scaling, attention in the semiconductor field has turned to graphene, a single layer of carbon atoms arranged in a honeycomb lattice. Its high mobility of charge carriers (electrons and holes) could lead to its use in the next generation of high-performance devices. Graphene is unlikely to replace silicon completely, however, because of the poor on/off current ratio resulting from its zero bandgap. But it could be used to improve silicon-based devices, in particular in high-speed electronics and optical modulators.

Two-dimensional free-space beam steering with an optical phased array on silicon-on-insulator

Abstract: We demonstrate a 16-channel, independently tuned waveguide surface grating optical phased array in silicon for two dimensional beam steering with a total field of view of 20° x 14°, beam width of 0.6° x 1.6°, and full-window background peak suppression of 10 dB.

Locally Oxidized Silicon Surface-Plasmon Schottky Detector for Telecom Regime

Abstract: We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Low loss silicon waveguides for the mid-infrared.

Abstract: Silicon-on-insulator (SOI) has been used as a platform for near-infrared photonic devices for more than twenty years. Longer wavelengths, however, may be problematic for SOI due to higher absorption loss in silicon dioxide. In this paper we report propagation loss measurements for the longest wavelength used so far on SOI platform. We show that propagation losses of 0.6-0.7 dB/cm can be achieved at a wavelength of 3.39 µm. We also report propagation loss measurements for silicon on porous silicon (SiPSi) waveguides at the same wavelength.

Hybrid Silicon Photonics for Optical Interconnects

Abstract: In this paper, we review the hybrid silicon photonic integration platform and its use for optical links. In this platform, a III/V layer is bonded to a fully processed silicon-on-insulator wafer. By changing the bandgap of the III/V quantum wells (QW), low-threshold-current lasers, high-speed modulators, and photodetectors can be fabricated operating at wavelengths of 1.55 μm. With a QW intermixing technology, these components can be integrated with each other and a complete high-speed optical interconnect can be realized on-chip. The hybrid silicon bonding and process technology are fully compatible with CMOS-processed wafers because high-temperature steps and contamination are avoided. Full wafer bonding is possible, allowing for low-cost and large-volume device fabrication.

Mid-infrared to telecom-band supercontinuum generation in highly nonlinear silicon-on-insulator wire waveguides

Abstract: We demonstrate the generation of a supercontinuum in a 2 cm long silicon wire by pumping the wire with mid-infrared picosecond pulses in the anomalous dispersion regime. The supercontinuum extends from 1535 nm up to 2525 nm for a coupled peak power of 12.7 W. It is shown that the supercontinuum originates primarily from the amplification of background noise. A detailed analysis of the spectral components which are generated through phase-matched processes is applied to extract the group velocity dispersion and fourth-order dispersion coefficient of the silicon wire waveguide.

Silicon-on-insulator polarization splitting and rotating device for polarization diversity circuits

Abstract: A compact and efficient polarization splitting and rotating device built on the silicon-on-insulator platform is introduced, which can be readily used for the interface section of a polarization diversity circuit. The device is compact, with a total length of a few tens of microns. It is also simple, consisting of only two parallel silicon-on-insulator wire waveguides with different widths, and thus requiring no additional and nonstandard fabrication steps. A total insertion loss of -0.6 dB and an extinction ratio of 12 dB have been obtained experimentally in the whole C-band.

High resolution on-chip spectroscopy based on miniaturized microdonut resonators

Abstract: We experimentally demonstrate a high resolution integrated spectrometer on silicon on insulator (SOI) substrate using a large-scale array of microdonut resonators. Through top-view imaging and processing, the measured spectral response of the spectrometer shows a linewidth of ~0.6 nm with an operating bandwidth of ~50 nm. This high resolution and bandwidth is achieved in a compact size using miniaturized microdonut resonators (radius ~2 μm) with a high quality factor, single-mode operation, and a large free spectral range. The microspectrometer is realized using silicon process compatible fabrication and has a great potential as a high-resolution, large dynamic range, light-weight, compact, high-speed, and versatile microspectrometer.

Polarization-independent grating couplers for silicon-on-insulator nanophotonic waveguides

Abstract: We propose the use of subwavelength structures in a waveguide grating to achieve polarization-independent coupling of light between an optical fiber and a silicon-on-insulator (SOI) optical waveguide. The subwavelength structure allows the mode effective indices of the TE and TM modes in the grating section to be precisely engineered. We calculate that coupling efficiency of over 64% is possible using the proposed design for polarization-independent coupling between single-mode optical fibers and SOI nanophotonic waveguides.

Development of SOI pixel process technology

Abstract: A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.

30GHz Ge electro-absorption modulator integrated with 3 μm silicon-on-insulator waveguide.

Abstract: We demonstrate a compact waveguide-based high-speed Ge electro-absorption (EA) modulator integrated with a single mode 3 µm silicon-on-isolator (SOI) waveguide. The Ge EA modulator is based on a horizontally-oriented p-i-n structure butt-coupled with a deep-etched silicon waveguide, which transitions adiabatically to a shallow-etched single mode large core SOI waveguide. The demonstrated device has a compact active region of 1.0 × 45 µm(2), a total insertion loss of 2.5-5 dB and an extinction ratio of 4-7.5 dB over a wavelength range of 1610-1640 nm with -4V(pp) bias. The estimated Δα/α value is in the range of 2-3.3. The 3 dB bandwidth measurements show that the device is capable of operating at more than 30 GHz. Clear eye-diagram openings at 12.5 Gbps demonstrates large signal modulation at high transmission rate.

Nanoscale MOS Transistors: Semi-Classical Transport and Applications

Abstract: 1. Introduction 2. Bulk semiconductors and the semi-classical model 3. Quantum confined inversion layers 4. Carrier scattering in silicon MOS transistors 5. The Boltzmann transport equation 6. The Monte Carlo method for the Boltzmann transport equation 7. Simulation of bulk and SOI silicon MOSFETs 8. MOS transistors with arbitrary crystal orientation 9. MOS transistors with strained silicon channels 10. MOS transistors with alternative materials Appendix A. Mathematical definitions and properties Appendix B. Integrals and transformations over a finite area A Appendix C. Calculation of the equi-energy lines with the k-p model Appendix D. Matrix elements beyond the envelope function approximation Appendix E. Charge density produced by a perturbation potential.

Integrated Circuit (IC) Chip Having Both Metal and Silicon Gate Field Effect Transistors (FETs) and Method of Manufacture

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs.

Methods for fabricating a finfet integrated circuit on a bulk silicon substrate

Abstract: Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.

An apodized SOI waveguide-to-fiber surface grating coupler for single lithography silicon photonics

Abstract: We present the design, fabrication, and characterization of a grating for coupling between a single mode silica fiber and the TE mode in a silicon photonic waveguide on a silicon on insulator (SOI) substrate. The grating is etched completely through the silicon device layer, thus permitting the fabrication of through-etched surface coupled silicon nanophotonic circuits in a single lithography step. Furthermore, the grating is apodized to match the diffracted wave to the mode profile of the fiber. We experimentally demonstrate a coupling efficiency of 35% with a 1 dB bandwidth of 47 nm at 1536 nm on a standard SOI substrate. Furthermore, we show by simulation that with an optimized buried oxide thickness, a coupling efficiency of 72% and a 1 dB bandwidth of 38 nm at 1550 nm is achievable. This is, to our knowledge, the highest simulated coupling efficiency for single-etch TE-mode grating couplers. In particular, simulations show that apodizing a conventional periodic through-etched grating decreases the back-reflection into the waveguide from 21% to 0.1%.

Device and Integration Technology for Silicon Photonic Transmitters

Abstract: The device and integration technology for silicon photonic transmitters are reviewed in this paper. The hybrid silicon platform enables on-chip lasers to be fabricated with silicon photonic circuits and can be integrated in the CMOS back-end flow. Laser arrays from multiple die bonding and quantum well intermixing techniques are demonstrated to extend the spectral bandwidth from the laser array of the transmitter. Two modulator technologies, silicon modulators and hybrid silicon modulators, are also described.

36 GHz submicron silicon waveguide germanium photodetector

Abstract: We present two effective approaches to improve the responsivity of high speed waveguide-based Ge photodetectors integrated on a 0.25μm silicon-on-insulator (SOI) platform. The main cause of poor responsivity is identified as metal absorption from the top contact to Ge. By optimizing Ge thickness and offsetting the contact window, we have demonstrated that the responsivity can be improved from 0.6A/W to 0.95A/W at 1550nm with 36GHz 3dB bandwidth. We also demonstrate that a wider device with double offset contacts can achieve 1.05A/W responsivity at 1550nm and 20GHz 3dB bandwidth.

Semiconductor-On-Insulator Materials for Nanoelectronics Applications

Abstract: New semiconductor-on-insulator materials.- Physics of modern SemOI devices.- Diagnostics of the SOI devices.- Sensors and MEMS on SOI.

Hybrid III-V semiconductor/silicon nanolaser

Abstract: Heterogeneous integration of III-V compound semiconductors on Silicon on Insulator is one the key technology for next-generation on-chip optical interconnects. In this context, the use of photonic crystals lasers represents a disruptive solution in terms of footprint, activation energy and ultrafast response. In this work, we propose and fabricate very compact laser sources integrated with a passive silicon waveguide circuitry. Using a subjacent Silicon-On-Insulator waveguide, the emitted light from a photonic crystal based cavity laser is efficiently captured. We study experimentally the evanescent wave coupling responsible for the funneling of the emitted light into the silicon waveguide mode as a function of the hybrid structure parameters, showing that 90% of coupling efficiency is possible.

Mid-infrared photonic crystal cavities in silicon.

Abstract: We demonstrate the design, fabrication, and characterization of silicon photonic crystal cavities realized in a silicon on insulator (SOI) platform, operating at a wavelength of 4.4 μm with a quality factor of 13,600. Cavity modes are imaged using the technique of scanning resonant scattering microscopy. To the best of our knowledge, this is the first demonstration of photonic devices fabricated in SOI and operating in the 4-5 μm wavelength range.

Efficient and compact TE–TM polarization converter built on silicon-on-insulator platform with a simple fabrication process

Abstract: An efficient TE–TM polarization converter built on a silicon-on-insulator nanophotonic platform is demonstrated. The strong cross-polarization coupling effect in air-cladded photonic-wire waveguides is employed to realize the conversion. A peak TE–TM coupling efficiency of 87% (−0.6 dB insertion loss) is measured experimentally. A polarization conversion efficiency of >92% with an overall insertion loss of <−1.6 dB is obtained in a wavelength range of 40 nm. The proposed device is compact, with a total length of 44 μm and can be fabricated with one lithography and etching step.

10 Gb/s operation of photonic crystal silicon optical modulators

Abstract: We report the first experimental demonstration of 10 Gb/s modulation in a photonic crystal silicon optical modulator. The device consists of a 200 μm-long SiO2-clad photonic crystal waveguide, with an embedded p-n junction, incorporated into an asymmetric Mach-Zehnder interferometer. The device is integrated on a SOI chip and fabricated by CMOS-compatible processes. With the bias voltage set at 0 V, we measure a VπL < 0.056 V∙cm. Optical modulation is demonstrated by electrically driving the device with a 231 − 1 bit non-return-to-zero pseudo-random bit sequence signal. An open eye pattern is observed at bitrates of 10 Gb/s and 2 Gb/s, with and without pre-emphasis of the drive signal, respectively.

Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs)

Abstract: This paper presents a two-dimensional analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Potential and electric field intensity calculated by Poisson’s equation are used to extract tunneling current values. The validity of the proposed model has been confirmed by comparing the analytical results with finite-element method (FEM) results.

High-performance 90° hybrid based on a silicon-on-insulator multimode interference coupler.

Abstract: We propose a multimode interference coupler (MMI) design for high-index-contrast technologies based on a shallowly etched multimode region, which is, for the first time to our knowledge, directly coupled to deeply etched input and output waveguides. This reduces the phase errors associated with the high-index contrast, while still allowing for a very compact layout. Using this structure, we fabricate a 2 × 4 MMI operating as a 90° hybrid, with a footprint of only 0.65 mm × 0.53 mm, including all the structures necessary to couple light to a fiber array. We experimentally demonstrate a common mode rejection ratio better than -20 dBe and phase errors better than ±5° in a ~50 nm bandwidth.

III-V compound semiconductors : integration with silicon-based microelectronics

Abstract: Part I: Basic Physical and Chemical Properties Fundamentals and the Future of Semiconductor Device Technology, M. Mastro The Challenge of III-V Materials Integration with Si Microelectronics, T. Li Part II: GaN and Related Alloys on Silicon Growth and Integration Techniques III-Nitrides on Si Substrate, J. Li, J.Y. Lin, H. Jiang, and N. Sawaki New Technology Approaches, A. Dadgar Part III: III-V Materials and Device Integration Processes with Si Microelectronics Group III-A Nitrides on Si: Stress and Microstructural Evolution, S. Raghavan and J.M. Redwing Direct Growth of III-V Devices on Silicon, T. Kazior, K.J. Herrick, and J. LaRoche Optoelectronic Device Integrated on Si, Di Liang and J.E. Bowers Reliability of III-V Electronic Devices, A.A. Immorlica, Jr. Part IV: Defect and Properties Evaluation and Characterization In Situ Curvature Measurements, Strains, and Stresses in the Case of Large Wafer Bending and Multilayer Systems, R. Clos and A. Krost X-Ray Characterization of Group III-Nitrides, A. Krost and J. Blasing Luminescence in GaN, F. Bertram Part V: Device Structures and Properties GaN-Based Optical Devices on Silicon, A. Dadgar The Conventional III-V Materials and Devices on Silicon, E.Y. Chang III-V Solar Cells on Silicon, S.A. Ringel and T.J. Grassman

RF Extraction of Self-Heating Effects in FinFETs

Abstract: Multigate semiconductor devices are celebrated for improved electrostatic control and reduced short-channel effects. However, nonplanar architectures suffer from increases of access resistances and capacitances, as well as self-heating effects due to confinement and increased phonon boundary scattering. In silicon-on-insulator (SOI) technology, the self-heating effects are aggravated by the presence of a thick buried oxide with low thermal conductivity, which prevents effective heat removal from the device active region to the Si substrate. Due to the shrinking of device dimensions in the nanometer scale, the thermal time constant that characterizes the dynamic self-heating is significantly reduced, and radio frequency extraction techniques are needed. The dynamic self-heating effect is characterized in n-channel SOI FinFETs, and the dependence of thermal resistance on FinFET geometry is discussed. It is experimentally confirmed that the fin width and the number of parallel fins are the most important parameters for thermal management in FinFETs, whereas fin spacing plays a less significant role.

Efficient broadband silicon-on-insulator grating coupler with low backreflection

Abstract: We design and fabricate an efficient broadband grating coupler on a 400 nm thick silicon-on-insulator wafer. The measured coupling loss is 3 dB when coupling to a single-mode fiber at 1310 nm wavelength with TE polarization. The spectral FWHM and backreflection are determined to be 58 nm and -27 dB, respectively.

Hybrid Silicon Laser Technology: A Thermal Perspective

Abstract: In this paper, the hybrid silicon laser integration platform is analyzed from a thermal perspective. Key laser performance limitations are identified under high temperature and high electrical power operating conditions. Particular attention is paid to the low thermal conductivity buried oxide layer that is utilized for optical confinement. A novel approach is presented and demonstrated to reduce the effect of the buried oxide and its application to a variety of thermally limited hybrid silicon devices is discussed.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s

Abstract: We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PICoff-chip for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 Vpp, the integrated 1 mm-phase-shifter modulator in the PICoff-chip demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of VπLπ ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at −1V. The fabricated silicon PICintra-chip for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PICintra-chip chip and 0.13μm CMOS interface IC chips were hybrid-integrated.