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Showing papers on "Silicon on insulator published in 2014"


Journal ArticleDOI
TL;DR: A rigorous approach for designing a highly efficient coupling between single mode optical fibers and silicon nanophotonic waveguides based on diffractive gratings based on cost-effective CMOS process flow is presented.
Abstract: We present a rigorous approach for designing a highly efficient coupling between single mode optical fibers and silicon nanophotonic waveguides based on diffractive gratings. The structures are fabricated on standard SOI wafers in a cost-effective CMOS process flow. The measured coupling efficiency reaches −1.08 dB and a record value of −0.62 dB in the 1550 nm telecommunication window using a uniform and a nonuniform grating, respectively, with a 1dB-bandwidth larger than 40 nm.

231 citations


Journal ArticleDOI
TL;DR: This article discusses the design of mid-IR chalcogenide waveguides integrated with polycrystalline PbTe detectors on a monolithic silicon platform for optical sensing, wherein the use of a low-index spacer layer enables the evanescent coupling ofMid-IR light from the waveguide to the detector.

218 citations


Journal ArticleDOI
TL;DR: The integration of germanium quantum-well devices and low-loss waveguides with silicon substrates shows promise for realizing low loss, on-chip photonic interconnects.
Abstract: The integration of germanium quantum-well devices and low-loss waveguides with silicon substrates shows promise for realizing low-loss, on-chip photonic interconnects.

203 citations


Journal ArticleDOI
TL;DR: In this paper, a resistive heater optimized for efficient and low-loss optical phase modulation in a silicon-on-insulator (SOI) waveguide was designed and a 61.6 μm long phase shifter was fabricated.
Abstract: We design a resistive heater optimized for efficient and low-loss optical phase modulation in a silicon-on-insulator (SOI) waveguide and characterize the fabricated devices. Modulation is achieved by flowing current perpendicular to a new ridge waveguide geometry. The resistance profile is engineered using different dopant concentrations to obtain localized heat generation and maximize the overlap between the optical mode and the high temperature regions of the structure, while simultaneously minimizing optical loss due to free-carrier absorption. A 61.6 μm long phase shifter was fabricated in a CMOS process with oxide cladding and two metal layers. The device features a phase-shifting efficiency of 24.77 ± 0.43 mW/π and a −3 dB modulation bandwidth of 130.0 ± 5.59 kHz; the insertion loss measured for 21 devices across an 8-inch wafer was only 0.23 ± 0.13 dB. Considering the prospect of densely integrated photonic circuits, we also quantify the separation necessary to isolate thermo-optic devices in the standard 220 nm SOI platform.

201 citations


Journal ArticleDOI
TL;DR: In this paper, the authors demonstrate nanophotonic circuits incorporating ferroelectric barium titanate (BaTiO3) thin films on the ubiquitous silicon-on-insulator (SOI) platform.
Abstract: The integration of complex oxides on silicon presents opportunities to extend and enhance silicon technology with novel electronic, magnetic, and photonic properties. Among these materials, barium titanate (BaTiO3) is a particularly strong ferroelectric perovskite oxide with attractive dielectric and electro-optic properties. Here we demonstrate nanophotonic circuits incorporating ferroelectric BaTiO3 thin films on the ubiquitous silicon-on-insulator (SOI) platform. We grow epitaxial, single-crystalline BaTiO3 directly on SOI and engineer integrated waveguide structures that simultaneously confine light and an RF electric field in the BaTiO3 layer. Using on-chip photonic interferometers, we extract a large effective Pockels coefficient of 213 ± 49 pm/V, a value more than six times larger than found in commercial optical modulators based on lithium niobate. The monolithically integrated BaTiO3 optical modulators show modulation bandwidth in the gigahertz regime, which is promising for broadband applications.

187 citations


Journal ArticleDOI
TL;DR: N nanophotonic circuits incorporating ferroelectric BaTiO3 thin films on the ubiquitous silicon-on-insulator (SOI) platform are demonstrated and show modulation bandwidth in the gigahertz regime, which is promising for broadband applications.
Abstract: The integration of complex oxides on silicon presents opportunities to extend and enhance silicon technology with novel electronic, magnetic, and photonic properties. Among these materials, barium titanate (BaTiO3) is a particularly strong ferroelectric perovskite oxide with attractive dielectric and electro-optic properties. Here we demonstrate nanophotonic circuits incorporating ferroelectric BaTiO3 thin films on the ubiquitous silicon-on-insulator (SOI) platform. We grow epitaxial, single-crystalline BaTiO3 directly on SOI and engineer integrated waveguide structures that simultaneously confine light and an RF electric field in the BaTiO3 layer. Using on-chip photonic interferometers, we extract a large effective Pockels coefficient of 213 plus minus 49 pm/V, a value more than six times larger than found in commercial optical modulators based on lithium niobate. The monolithically integrated BaTiO3 optical modulators show modulation bandwidth in the gigahertz regime, which is promising for broadband applications.

186 citations


Journal ArticleDOI
TL;DR: In this article, the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration.
Abstract: The current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes In particular, for several established research and development foundries that grant general access, silicon-on-insulator wafers with a silicon thickness of 220 nm have become the standard substrate for which devices and circuits have to be designed In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration We find that in all devices considered there is an advantage in using a silicon thickness larger than 220 nm, either for improved performance or for simplified fabrication processes and relaxed tolerances

176 citations


Journal ArticleDOI
TL;DR: In this paper, an integrated hybrid III-V/Si laser with two integrated intra-cavity ring resonators is presented, achieving high extinction ratio from 6 to 10 dB and excellent bit error rate performance at 10 Gb/s.
Abstract: This paper summarizes recent advances of integrated hybrid InP/SOI lasers and transmitters based on wafer bonding. At first the integration process of III-V materials on silicon is described. Then the paper reports on the results of single wavelength distributed Bragg reflector lasers with Bragg gratings etched on silicon waveguides. We then demonstrate that, thanks to the high-quality silicon bend waveguides, hybrid III-V/Si lasers with two integrated intra-cavity ring resonators can achieve a wide thermal tuning range, exceeding the C band, with a side mode suppression ratio higher than 40 dB. Moreover, a compact array waveguide grating on silicon is integrated with a hybrid III-V/Si gain section, creating a wavelength-selectable laser source with 5 wavelength channels spaced by 400 GHz. We further demonstrate an integrated transmitter with combined silicon modulators and tunable hybrid III-V/Si lasers. The integrated transmitter exhibits 9 nm wavelength tunability by heating an intra-cavity ring resonator, high extinction ratio from 6 to 10 dB, and excellent bit-error-rate performance at 10 Gb/s.

174 citations


Proceedings ArticleDOI
TL;DR: In this paper, the authors report on recent advances on integrated hybrid InP/SOI lasers and transmitters using a wafer bonding technique made in particular at III-V Lab, France.
Abstract: Silicon photonics is attracting large attention due to the promise of fabricating low-cost, compact circuits that integrate photonic and microelectronic elements. It can address a wide range of applications from short distance data communication to long haul optical transmission. Today, practical Si-based light sources are still missing, despite the recent demonstration of an optically pumped germanium laser. This situation has driven research to the heterogeneous integration of III-V semiconductors on silicon through wafer bonding techniques. This paper reports on recent advances on integrated hybrid InP/SOI lasers and transmitters using a wafer bonding technique made in particular at III-V Lab, France.

141 citations


Journal ArticleDOI
TL;DR: The implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology are presented.
Abstract: This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.

138 citations


Journal ArticleDOI
TL;DR: The modulator shows a modulation depth of 16 dB and an insertion loss of 3.3 dB, surpassing GeSi and previous graphene based absorption modulators and being comparable to silicon Mach-Zehnder interferometer based modulators.
Abstract: Graphene is considered a promising material for broadband opto-electronics because of its linear and gapless band structure. Its optical conductivity can be significantly tuned electrostatically by shifting the Fermi level. Using mentioned property, we experimentally demonstrate a graphene based electro-absorption modulator with very low insertion loss. The device is realized on a silicon on insulator (SOI) waveguide operating at 1550 nm wavelength. The modulator shows a modulation depth of 16 dB and an insertion loss of 3.3 dB, surpassing GeSi and previous graphene based absorption modulators and being comparable to silicon Mach-Zehnder interferometer based modulators.

Journal ArticleDOI
TL;DR: Fiber-to-chip grating couplers with aligned silicon nitride (Si(3)N(4)) and silicon (Si) grating teeth for wide bandwidths and high coupling efficiencies without the use of bottom reflectors are proposed and experimentally demonstrated.
Abstract: We propose and experimentally demonstrate fiber-to-chip grating couplers with aligned silicon nitride (Si(3)N(4)) and silicon (Si) grating teeth for wide bandwidths and high coupling efficiencies without the use of bottom reflectors. The measured 1-dB bandwidth is a record 80 nm, and the measured peak coupling efficiency is -1.3 dB, which is competitive with the best Si-only grating couplers. The grating couplers are integrated in a Si(3)N(4) on silicon-on-insulator (SOI) integrated optics platform with aligned waveguides in both the Si(3)N(4) and Si, and we demonstrate a 1 × 4 tunable multiplexer/demultiplexer using the Si(3)N(4)-on-SOI dual-level grating couplers and thermally-tuned Si microring resonators.

Journal ArticleDOI
TL;DR: In this paper, a silicon-based photonic integrated circuit technology for applications beyond the telecommunication wavelength range is discussed, where the strong nonlinearity of silicon combined with the low nonlinear absorption in the mid-infrared is exploited to generate picosecond pulse based supercontinuum sources, optical parametric oscillators and wavelength translators connecting the tele communication wavelength range and the midinfrared.
Abstract: In this paper we discuss silicon-based photonic integrated circuit technology for applications beyond the telecommunication wavelength range. Silicon-on-insulator and germanium-on-silicon passive waveguide circuits are described, as well as the integration of III-V semiconductors, IV-VI colloidal nanoparticles and GeSn alloys on these circuits for increasing the functionality. The strong nonlinearity of silicon combined with the low nonlinear absorption in the mid-infrared is exploited to generate picosecond pulse based supercontinuum sources, optical parametric oscillators and wavelength translators connecting the telecommunication wavelength range and the mid-infrared.

Journal ArticleDOI
TL;DR: In this paper, a resistive heater optimized for efficient and low-loss optical phase modulation in a silicon-on-insulator (SOI) waveguide was designed and fabricated.
Abstract: We design a resistive heater optimized for efficient and low-loss optical phase modulation in a silicon-on-insulator (SOI) waveguide and characterize the fabricated devices. Modulation is achieved by flowing current perpendicular to a new ridge waveguide geometry. The resistance profile is engineered using different dopant concentrations to obtain localized heat generation and maximize the overlap between the optical mode and the high temperature regions, while simultaneously minimizing optical loss due to free-carrier absorption. A 61.6 micrometer-long phase shifter was fabricated in a CMOS process with oxide cladding and two metal layers. The device features a phase-shifting efficiency of 24.77 +/- 0.43 mW/pi and a -3 dB modulation bandwidth of 130.0 +/- 5.59 kHz. The insertion loss measured for 21 devices across an 8-inch wafer was only 0.23 +/- 0.13 dB. Considering the prospect of densely integrated photonic circuits, we also quantify the separation necessary to isolate thermo-optic devices in the standard 220 nm SOI platform.

Journal ArticleDOI
TL;DR: It is argued, based on arguments of energy efficiency and energy proportionality, that on-chip sources provide a dramatic overall system efficiency improvement, as compared to using an off-chip (comb) source.
Abstract: Silicon photonics is the prime candidate technology to realize an optical network-on-chip for global interconnects in future multi-core processors. Since silicon photonics lacks efficient native-substrate optical sources, the question is whether off-chip or heterogeneously integrated on-chip sources are the preferred technology. In this paper we argue, based on arguments of energy efficiency and energy proportionality, that on-chip sources provide a dramatic overall system efficiency improvement, as compared to using an off-chip (comb) source. We estimate an increase in source efficiency for on-chip lasers of close to 20 dB. These results provide a clear case to include on-chip lasers, such as hybrid silicon lasers, into the network architecture design.

Journal ArticleDOI
TL;DR: The design and fabrication of a two-mode SOI ring resonator for MDM systems on SOI is presented, demonstrating a signal-to-crosstalk ratio above 18 dB for both modes at the through and drop ports and concluding that the ring resonators has the potential for filtering and switching.
Abstract: Mode-division multiplexing (MDM) is an emerging multiple-input multiple-output method, utilizing multimode waveguides to increase channel numbers. In the past, silicon-on-insulator (SOI) devices have been primarily focused on single-mode waveguides. We present the design and fabrication of a two-mode SOI ring resonator for MDM systems. By optimizing the device parameters, we have ensured that each mode is treated equally within the ring. Using adiabatic Bezier curves in the ring bends, our ring demonstrated a signal-to-crosstalk ratio above 18 dB for both modes at the through and drop ports. We conclude that the ring resonator has the potential for filtering and switching for MDM systems on SOI.

Journal ArticleDOI
TL;DR: A low-loss CMOS-compatible multi-layer platform using monolithic back-end-of-line (BEOL) integration is demonstrated, achieving less than 0.2dB/transition loss across 70nm bandwidth, the lowest inter-layer transition loss ever reported.
Abstract: We demonstrated a low-loss CMOS-compatible multi-layer platform using monolithic back-end-of-line (BEOL) integration. 0.8dB/cm propagation loss is measured for the PECVD Si3N4 waveguide at 1580nm wavelength. The loss is further reduced to 0.24dB/cm at 1270nm wavelength, justifying the platform’s feasibility for O-band operation. An inter-layer transition coupler is designed, achieving less than 0.2dB/transition loss across 70nm bandwidth. This is the lowest inter-layer transition loss ever reported. A thermally tuned micro-ring filter is also integrated on the platform, with performance comparable to similar device on SOI platform.

Journal ArticleDOI
06 Nov 2014-ACS Nano
TL;DR: The capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates are reported.
Abstract: Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, posi...

Journal ArticleDOI
TL;DR: Novel polarization management devices in a custom-designed silicon nitride (Si(3)N(4)) waveguides on silicon-on-insulator (SOI) integrated photonics platform are demonstrated.
Abstract: We demonstrate novel polarization management devices in a custom-designed silicon nitride (Si(3)N(4)) on silicon-on-insulator (SOI) integrated photonics platform. In the platform, Si(3)N(4) waveguides are defined atop silicon waveguides. A broadband polarization rotator-splitter using a TM0-TE1 mode converter in a composite Si(3)N(4)-silicon waveguide is demonstrated. The polarization crosstalk, insertion loss, and polarization dependent loss are less than -19 dB, 1.5 dB, and 1.0 dB, respectively, over a bandwidth of 80 nm. A polarization controller composed of polarization rotator-splitters, multimode interference couplers, and thin film heaters is also demonstrated.

Journal ArticleDOI
TL;DR: In this paper, the authors developed a two dimensional analytical model for surface potential and drain current for a long channel dual material gate (DMG) Silicon-on-Insulator (SOI) tunneling field effect transistor (TFET) without assuming a fully depleted channel.
Abstract: In this paper we have developed a two dimensional (2D) analytical model for surface potential and drain current for a long channel Dual Material Gate (DMG) Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using two-dimensional numerical simulations. In comparison to the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (ION), a better ON-state to OFF-state current (ION/IOFF) ratio and a better sub-threshold slope (SS).

Proceedings ArticleDOI
09 Jun 2014
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Abstract: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

Journal ArticleDOI
03 Feb 2014-ACS Nano
TL;DR: This paper shows monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry's most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process.
Abstract: In today’s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry’s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage ...

Proceedings ArticleDOI
TL;DR: In this article, the authors describe their efforts to improve the performance of SOI-based biosensors, specifically, TE and TM mode microring resonators, thin waveguide resonators and sub-wavelength grating resonators.
Abstract: Silicon photonics biosensors continue to be an area of active research, showing the potential to revolutionize Labon-Chip applications ranging from environmental monitoring to medical diagnostics. As near-infrared light propagates through nano-scale silicon wires on an SOI chip, a portion of the light resides outside the waveguide and interacts with biomolecules and the biological matrix on the waveguide’s surface. This capability makes silicon photonics an ideal platform for label-free biosensing. Additionally, the SOI platform is compatible with standard CMOS fabrication processes, facilitating manufacturing at the economies of scale offered by today’s foundries. In this paper, we describe our efforts to improve the performance of SOI-based biosensors—specifically, TE and TM mode microring resonators, thin waveguide resonators, sub-wavelength grating resonators, as well as strip and slot Bragg gratings. We compare device performance in terms of sensitivity, intrinsic limit of detection, and their potential for biosensing applications in Lab-on-Chip systems.

Journal ArticleDOI
TL;DR: A multi-drive stacked- FET approach is proposed to improve the output power and efficiency of stacked-FET power amplifiers in 45 nm SOI CMOS above 60 GHz and an analysis of conventional and multi- Drive PAs demonstrates the performance improvement.
Abstract: Gate resistance significantly limits the output power and power-added efficiency of stacked-FET power amplifiers in 45 nm SOI CMOS above 60 GHz. A multi-drive stacked-FET approach is proposed to improve the output power and efficiency. An analysis of conventional and multi-drive stacked-FET PAs demonstrates the performance improvement. A multi-drive three-stack PA is implemented in 45 nm SOI CMOS for 90 GHz operation occupying 0.23 mm 2 . This PA achieves more than 19 dBm output power with peak PAE of 14% and 12 dB gain at 90 GHz using a 3.4 V power supply.

Journal ArticleDOI
TL;DR: A highly efficient silicon (Si) hybrid external cavity laser with a wavelength tunable ring reflector is fabricated on a complementary metal-oxide semiconductor (CMOS)-compatible Si-on-insulator (SOI) platform and experimental results with high output power are demonstrated.
Abstract: A highly efficient silicon (Si) hybrid external cavity laser with a wavelength tunable ring reflector is fabricated on a complementary metal-oxide semiconductor (CMOS)-compatible Si-on-insulator (SOI) platform and experimental results with high output power are demonstrated. A III-V semiconductor gain chip is edge-coupled into a SOI cavity chip through a SiNx spot size converter and Si grating couplers are incorporated to enable wafer-scale characterization. The laser output power reaches 20 mW and the highest wall-plug efficiency of 7.8% is measured at 17.3 mW in un-cooled condition. The laser wavelength tuning ranges are 8 nm for the single ring reflector cavity and 35 nm for the vernier ring reflector cavity, respectively. The Si hybrid laser is a promising light source for energy-efficient Si CMOS photonic links.

Journal ArticleDOI
TL;DR: The realization of an optical sensor based on an infiltrated high-Q slot photonic crystal cavity in a nonfreestanding membrane configuration that allows a straightforward integration in the silicon photonics platform, while providing a compliant mechanical stability.
Abstract: We present the realization of an optical sensor based on an infiltrated high-Q slot photonic crystal cavity in a nonfreestanding membrane configuration. Successive infiltrations by liquids with refractive indices ranging from 1.345 to 1.545 yield a sensitivity S of 235 nm/RIU (refractive index unit), while the Q-factor is comprised between 8000 and 25,000, giving a sensor figure of merit up to 3700. This sensor has a detection limit of 1.25×10−5. The operation of this device on a silicon-on-insulator (SOI) substrate allows a straightforward integration in the silicon photonics platform, while providing a compliant mechanical stability.

Journal ArticleDOI
TL;DR: In this article, anisotropic wet etching was used to create atomically sharp V-shaped grooves for junctionless FETs, where the channel length, defined as the width of the V-groove bottom, was as short as 3 nm and the channel thickness was between 1 and 8 nm.
Abstract: Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching. The channel length, defined as the width of the V-groove bottom, was as short as 3 nm, and the channel thickness was between 1 and 8 nm. Excellent transistor characteristics with threshold voltages that are optimal for low-power operation were obtained for both n-FETs and p-FETs when the thickness of both the channel and gate dielectric film thickness was reduced to 1 nm. The origin of the excellent electrostatic control is discussed on the basis of fringe capacitance and quantum confinement effects in a nanometer-scale ultrathin Si layer where band-gap expansion, dielectric constant reduction, and increase in the dopant activation energy become prominent. The electrical characteristics of the ultrashort channel JL-FETs were found to be very sensitive to device parameters such as the channel thickness and dopant concentration.

Journal ArticleDOI
TL;DR: Design and simulation results are presented for an ultralow switching energy, resonator based, silicon-on-insulator (SOI) electro-optical modulator that allows for a 6 dB extinction ratio at telecom wavelengths with an energy cost as low as 14 attojoules/bit.
Abstract: Design and simulation results are presented for an ultralow switching energy, resonator based, silicon-on-insulator (SOI) electro-optical modulator. The nanowire waveguide and Q ~8500 resonator are seamlessly integrated via a high-transmission tapered 1D photonic crystal cavity waveguide structure. A lateral p-n junction of modulation length Lm ~λ is used to alter the index of refraction and, therefore, shift the resonance wavelength via fast carrier depletion. Differential signaling of the device with ΔV ~0.6 Volts allows for a 6dB extinction ratio at telecom wavelengths with an energy cost as low as 14 attojoules/bit.

Journal ArticleDOI
TL;DR: Using wafer-scale measurements of structures fabricated in the IMEC Standard Passives process, the normalized standard deviation in the per-length coupling coefficient of the variation-tolerant directional couplers is up to 4 times smaller than that of strip waveguide designs.
Abstract: We design silicon ridge/rib waveguide directional couplers which are simultaneously tolerant to width, height, coupling gap, and etch depth variations. Using wafer-scale measurements of structures fabricated in the IMEC Standard Passives process, we demonstrate the normalized standard deviation in the per-length coupling coefficient (a metric for the splitting ratio variation) of the variation-tolerant directional couplers is up to 4 times smaller than that of strip waveguide designs. The variation-tolerant couplers are also the most broadband and the deviation in the coupling coefficient shows the lowest spectral dependence.

Journal ArticleDOI
TL;DR: The common approach used to minimize the waveguide effective modal area does not accurately predict the configuration with the maximum nonlinear parameter, and ultra-large nonlinear parameters made such waveguides promising platforms for nonlinear integrated optics at ultra-low powers, and for previously unobserved nonlinear optical effects to be studied in a waveguide platform.
Abstract: Mono-layer graphene integrated with optical waveguides is studied for the purpose of maximizing E-field interaction with the graphene layer, for the generation of ultra-large nonlinear parameters. It is shown that the common approach used to minimize the waveguide effective modal area does not accurately predict the configuration with the maximum nonlinear parameter. Both photonic and plasmonic waveguide configurations and graphene integration techniques realizable with today’s fabrication tools are studied. Importantly, nonlinear parameters exceeding 104 W−1/m, two orders of magnitude larger than that in silicon on insulator waveguides without graphene, are obtained for the quasi-TE mode in silicon waveguides incorporating mono-layer graphene in the evanescent part of the optical field. Dielectric loaded surface plasmon polariton waveguides incorporating mono-layer graphene are observed to generate nonlinear parameters as large as 105 W−1/m, three orders of magnitude larger than that in silicon on insulator waveguides without graphene. The ultra-large nonlinear parameters make such waveguides promising platforms for nonlinear integrated optics at ultra-low powers, and for previously unobserved nonlinear optical effects to be studied in a waveguide platform.