Showing papers on "Silicon on insulator published in 2015"
TL;DR: In this paper, the authors present results from multilayer silicon nitride (SiN) on silicon-on-insulator (SOI) integrated photonic platforms over the telecommunication wavelength bands near 1550 and 1310 nm.
Abstract: We review and present additional results from our work on multilayer silicon nitride (SiN) on silicon-on-insulator (SOI) integrated photonic platforms over the telecommunication wavelength bands near 1550 and 1310 nm. SiN-on-SOI platforms open the possibility for passive optical functionalities implemented in the SiN layer to be combined with active functionalities in the SOI. SiN layers can be integrated onto SOI using a front-end or back-end of line integration process flow. These photonic platforms support low-loss SiN waveguides, low-loss and low-crosstalk waveguide crossings, and low-loss interlayer transitions using adiabatic tapers. Novel ultra-broadband and efficient grating couplers as well as polarization management devices are enabled by the close coupling between the silicon and SiN layers.
183 citations
TL;DR: This work reports on a grating coupler with sub-decibel experimental coupling efficiency using a single etch process in a standard 220-nm silicon-on-insulator (SOI) platform, and demonstrates a subwavelength metamaterial refractive index engineered nanostructure with backside metal reflector.
Abstract: Surface grating couplers are fundamental components in chip-based photonic devices to couple light between photonic integrated circuits and optical fibers. In this work, we report on a grating coupler with sub-decibel experimental coupling efficiency using a single etch process in a standard 220-nm silicon-on-insulator (SOI) platform. We specifically demonstrate a subwavelength metamaterial refractive index engineered nanostructure with backside metal reflector, with the measured peak fiber-chip coupling efficiency of -0.69 dB (85.3%) and 3 dB bandwidth of 60 nm. This is the highest coupling efficiency hitherto experimentally achieved for a surface grating coupler implemented in 220-nm SOI platform.
113 citations
TL;DR: Numerical results show that extremely large optical confinement factor of the tested analytes can be obtained by DSHP waveguide with optimized geometrical parameters, which is larger than both, conventional SOI waveguides and plasmonic slot waveguide with same widths.
Abstract: A Mach-Zehnder Interferometer (MZI) liquid sensor, employing ultra-compact double-slot hybrid plasmonic (DSHP) waveguide as active sensing arm, is developed. Numerical results show that extremely large optical confinement factor of the tested analytes (as high as 88%) can be obtained by DSHP waveguide with optimized geometrical parameters, which is larger than both, conventional SOI waveguides and plasmonic slot waveguides with same widths. As for MZI sensor with 40μm long DSHP active sensing area, the sensitivity can reach as high value as 1061nm/RIU (refractive index unit). The total loss, excluding the coupling loss of the grating coupler, is around 4.5dB.
103 citations
TL;DR: In this article, the authors identify the common temperature measuring techniques, and focus on the use and advantages offered by silicon diodes operated as temperature sensors in different drive modes, and explore the published literature for summarizing the application areas where such sensors have been utilized successfully in recent years.
Abstract: Most of the variables measured in scientific investigations or engineering applications depend, by varying degrees, on temperature. This necessitates the simultaneous measurement of temperature along with the variable of interest in order to perform high fidelity temperature compensated measurements. Silicon diode based temperature sensors (or silicon thermodiodes) have the advantages of being low cost, having an absolute temperature measurement capability as well as providing the option of on-chip integration with electronic circuits and a wide temperature measurement range. Leveraging these advantages, engineers and scientists have used silicon thermodiodes in numerous and diverse applications. This paper identifies the common temperature measuring techniques, and focuses on the use and advantages offered by silicon diodes operated as temperature sensors in different drive modes. Finally it explores the published literature for summarizing the application areas where such sensors have been utilized successfully in recent years.
102 citations
TL;DR: It is shown that the proposed devices may theoretically outperform existing modulators both in terms of V(π)L and of insertion losses.
Abstract: In this paper we report on an electro-refractive modulator based on single or double-layer graphene on top of silicon waveguides. The graphene layers are biased to the transparency condition in order to achieve phase modulation with negligible amplitude modulation. By means of a detailed study of both the electrical and optical properties of graphene and silicon, as well as through optimization of the geometrical parameters, we show that the proposed devices may theoretically outperform existing modulators both in terms of VπL and of insertion losses. The overall figures of merit of the proposed devices are as low as 8.5 and 2dB∙V for the single and double layer cases, respectively.
97 citations
TL;DR: In this paper, the authors report the potential benefits of dopingless double-gate field effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications.
Abstract: In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at $V_{\rm DD} = 0.8$ V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.
81 citations
16 Jun 2015
TL;DR: In this paper, the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO).
Abstract: We report on the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. It enables the fabrication of InGaAs-OI starting from both bulk and SOI Si wafers. The InGaAs epitaxial structures are characterized by a very low defectivity, and can fulfill the requirements of both ultra-thin-body and fins-based advanced CMOS nodes. Gate-first self-aligned FinFETs (100-nm-long gate, 50-nm-wide fins and 250-nm-wide plug-contacts) with excellent electrical characteristics comparable to start-of-the-art InGaAs MOSFETs on Si are demonstrated, highlighting that this new concept has significant potential to enable introduction of high-mobility channel materials in high-volume manufacturing of advanced CMOS nodes.
75 citations
TL;DR: An electrically pumped hybrid cavity AlGaInAs-silicon long-wavelength VCSEL using a high contrast grating (HCG) reflector on a silicon-on-insulator (SOI) substrate using a novel HCG-VCSEL design that may enable low cost light sources for integrated optical links.
Abstract: We report an electrically pumped hybrid cavity AlGaInAs-silicon long-wavelength VCSEL using a high contrast grating (HCG) reflector on a silicon-on-insulator (SOI) substrate. The VCSEL operates at silicon transparent wavelengths ~1.57 μm with >1 mW CW power outcoupled from the semiconductor DBR, and single-mode operation up to 65 °C. The thermal resistance of our device is measured to be 1.46 K/mW. We demonstrate >2.5 GHz 3-dB direct modulation bandwidth, and show error-free transmission over 2.5 km single mode fiber under 5 Gb/s direct modulation. We show a theoretical design of SOI-HCG serving both as a VCSEL reflector as well as waveguide coupler for an in-plane SOI waveguide, facilitating integration of VCSEL with in-plane silicon photonic circuits. The novel HCG-VCSEL design, which employs scalable flip-chip eutectic bonding, may enable low cost light sources for integrated optical links.
74 citations
TL;DR: In this paper, a widebandgap (WBG) semiconductor is proposed to replace the traditional silicon-based power conversion for power electronic devices, which can achieve improved efficiency, reduced size, and lower overall system cost.
Abstract: For several decades, silicon (Si) has been the primary semiconductor choice for power electronic devices. During this time, the development and fabrication of Si devices has been optimized, which, in combination with the large abundance of material, has resulted in high manufacturing capability and extremely low costs. However, Si is approaching its limits in power conversion [1], [2]; improved efficiency, reduced size, and lower overall system cost can now be achieved by replacing Si devices with wide-bandgap (WBG) semiconductors [1]?[3].
72 citations
TL;DR: In this article, an electrostatically driven bi-axial micro-scanner with capacitive position sensing for Lissajous scanning projection is presented, where a PLL (phase-locked loop)-based oscillator loop is developed to sustain mechanical resonance and to provide mirror position information.
Abstract: Bi-axial or two-dimensional (2D) MEMS micro-scanning mirrors (or micro-scanners) are considered the key component for laser scanning projectors. Many studies have shown the mechanical characterization of fabricated devices driven by various mechanisms. This work presents an electrostatically driven bi-axial micro-scanner with capacitive position sensing for Lissajous scanning projection. With the added sensing capability, a PLL (phase-locked loop)-based oscillator loop is developed to sustain mechanical resonance and to provide mirror position information, which are equally important for practical applications. The micro-scanner and the required circuits are implemented using bulk micromachining SOI (silicon on insulator) and 0.35-μm CMOS (complementary metal oxide semiconductor) technologies, respectively. The measured resonant frequencies of the bi-axial micro-scanner for the slow and fast-axis scans are 1.4 and 21.9 kHz, and the associated optical scan angles are 22.5° and 40°, respectively, under pulse modulation of 48 and 115 V pp . The fabricated micro-scanner is adopted in a laser beam scanning projection system to achieve WVGA (852 × 480) display resolution.
70 citations
TL;DR: In this paper, theoretical designs and simulations of electrooptical 2 × 2 switches and 1 × 1 loss modulators based upon GST-embedded SOI channel waveguides are presented.
Abstract: This paper reports theoretical designs and simulations of electrooptical 2 × 2 switches and 1 × 1 loss modulators based upon GST-embedded SOI channel waveguides. It is assumed that the amorphous and crystalline phases of GST can be triggered electrically by Joule heating current applied to a 10-nm GST film sandwiched between doped-Si waveguide strips. TEo and TMo mode effective indices are calculated over 1.3 to 2.1-μm wavelength range. For 2 × 2 Mach–Zehnder and directional coupler switches, low insertion loss, low crosstalk, and short device lengths are predicted for 2.1 μm, although a decreased performance is projected for 1.55 μm. For 1.3–2.1 μm, the 1 × 1 EO waveguide has application as a variable optical attenuator and as a digital modulator, albeit with ≦100-ns state-transition time. Because the active material has two “stable” phases, the device holds itself in either state, and voltage needs to be applied only during transition.
22 Mar 2015
TL;DR: A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated and process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.
Abstract: A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.
TL;DR: In this article, the authors demonstrate 16-state quadrature amplitude modulation (16QAM) signals at a symbol rate of 40 GBd using silicon-based modulators.
Abstract: We demonstrate for the first time generation of 16-state quadrature amplitude modulation (16QAM) signals at a symbol rate of 40 GBd using silicon-based modulators. Our devices exploit silicon-organic hybrid integration, which combines silicon-on-insulator slot waveguides with electro-optic cladding materials to realize highly efficient phase shifters. The devices enable 16QAM signaling and quadrature phase shift keying at symbol rates of 40 GBd and 45 GBd, respectively, leading to line rates of up to 160 Gb/s on a single wavelength and in a single polarization. This is the highest value demonstrated by a silicon-based device up to now. The energy consumption for 16QAM signaling amounts to less than 120 fJ/bit—one order of magnitude below that of conventional silicon photonic 16QAM modulators.
TL;DR: In this paper, the authors report about design, fabrication, and testing of echelle grating demultiplexers in the O-band for silicon-based photonic integrated circuits.
Abstract: In this letter, we report about design, fabrication, and testing of echelle grating (EG) demultiplexers in the O-band (1.31- $\mu $ m) for silicon-based photonic integrated circuits. In detail, flat band perfectly chirped EGs and two-point stigmatic EGs on the 300-nm thick silicon-on-insulator platform designed for $4\times 800$ -GHz spaced wavelength-division multiplexing featuring a low average crosstalk (−30 dB), a precise channel spacing, optimized interchannel uniformity (0.7 dB) and insertion losses (3–3.5 dB) are presented. Wafer-level statistical performance analysis shows the EG spectral response to be stable over the wafer in terms of crosstalk, channel spacing, and bandwidth with minimal wavelength dispersion (<0.8 nm), thus highlighting the intrinsic robustness of high-order gratings and chosen fab pathways as well as the full reliability of 3-D vectorial modeling tools.
TL;DR: An inverse taper on silicon is proposed and designed to realize an efficient mode converter available for the connection between multimode silicon nanophotonic integrated circuits and few-mode fibers to make multi-chip mode (de)multiplexers available to work together with few- mode fibers in the future.
Abstract: An inverse taper on silicon is proposed and designed to realize an efficient mode converter available for the connection between multimode silicon nanophotonic integrated circuits and few-mode fibers. The present mode converter has a silicon-on-insulator inverse taper buried in a 3 × 3μm(2) SiN strip waveguide to deal with not only for the fundamental mode but also for the higher-order modes. The designed inverse taper enables the conversion between the six modes (i.e., TE(11), TE(21), TE(31), TE(41), TM(11), TM(12)) in a 1.4 × 0.22μm(2) multimode SOI waveguide and the six modes (like the LP(01), LP(11a), LP(11b) modes in a few-mode fiber) in a 3 × 3μm(2) SiN strip waveguide. The conversion efficiency for any desired mode is higher than 95.6% while any undesired mode excitation ratio is lower than 0.5%. This is helpful to make multimode silicon nanophotonic integrated circuits (e.g., the on-chip mode (de)multiplexers developed well) available to work together with few-mode fibers in the future.
TL;DR: The present hybrid (de)multiplexer can operate for both TE- and TM- polarizations and thus is available for PDM-WDM systems.
Abstract: A compact silicon hybrid (de)multiplexer is designed and demonstrated by integrating a single bi-directional AWG with a polarization diversity circuit, which consists of an ultra-short polarization-beam splitter (PBS) based on a bent coupler and a polarization rotator (PR) based on a silicon-on-insulator nanowire with a cut corner. The present hybrid (de)multiplexer can operate for both TE- and TM- polarizations and thus is available for PDM-WDM systems. An 18-channel hybrid (de)multiplexer is realized with 9 wavelengths as an example. The wavelength-channel spacing is 400GHz (i.e., Δλch = 3.2nm) and the footprint of the device is about 530μm × 210μm. The channel crosstalk is about −13dB and the total excess loss is about 7dB. The excess loss increases by about 1~2dB due to the cascaded polarization diversity circuit in comparison with a single bi-directional AWG.
20 Apr 2015
TL;DR: In this article, the design and characterization of highly directional vertical grating couplers achieving −1.2 dB coupling efficiency with 78nm 1-dB bandwidth realized in a commercially available 45nm microelectronics SOI process is presented.
Abstract: We present the design and characterization of highly directional vertical grating couplers achieving −1.2 dB coupling efficiency with 78nm 1- dB bandwidth realized in a commercially available 45nm microelectronics SOI process.
TL;DR: The photolithographic fabrication of high-Q silica-clad PhC-NCs will open possibility for mass-manufacturing and boost the fusion between silicon photonics and CMOS devices.
Abstract: Progress on the fabrication of ultrahigh-Q photonic-crystal nanocavities (PhC-NCs) has revealed the prospect for new applications including silicon Raman lasers that require a strong confinement of light. Among various PhC-NCs, the highest Q has been recorded with silicon. On the other hand, microcavity is one of the basic building blocks in silicon photonics. However, the fusion between PhC-NCs and silicon photonics has yet to be exploited, since PhC-NCs are usually fabricated with electron-beam lithography and require an air-bridge structure. Here we show that a 2D-PhC-NC fabricated with deep-UV photolithography on a silica-clad silicon-on-insulator (SOI) structure will exhibit a high-Q of 2.2 × 105 with a mode-volume of ~1.7(λ/n)3. This is the highest Q demonstrated with photolithography. We also show that this device exhibits an efficient thermal diffusion and enables high-speed switching. The demonstration of the photolithographic fabrication of high-Q silica-clad PhC-NCs will open possibility for mass-manufacturing and boost the fusion between silicon photonics and CMOS devices.
TL;DR: A class of low-loss guiding schemes by integrating silicon-on-insulator (SOI) waveguides with plasmon nanowire structures is introduced, which demonstrates improved guiding properties compared to the conventional hybrid and nanowirespun polaritons.
Abstract: The simultaneous realization of nanoscale field localization and low transmission loss remains one of the major challenges in nanophotonics. Metal nanowire waveguides can fulfill this goal to a certain extent by confining light within subwavelength space, yet their optical performances are still restricted by the tradeoff between confinement and loss, which results in quite limited propagation distances when their mode sizes are reduced down to the nanometer scale. Here we introduce a class of low-loss guiding schemes by integrating silicon-on-insulator (SOI) waveguides with plasmon nanowire structures. The closely spaced silicon and metal configurations allow efficient light squeezing within the nanometer, low-index silica gaps between them, enabling deep-subwavelength light transmission with low modal attenuation. Optimizations of key structural parameters unravel the wide-range existence of the high-performance hybrid nanowire plasmon mode, which demonstrates improved guiding properties compared to the conventional hybrid and nanowire plasmon polaritons. The excitation strategy of the guided mode and the feasibility of the waveguide for compact photonic integration as well as active components are also discussed to lay the foundation for its practical implementation. The remarkable properties of these metallic-nanowire-loaded SOI waveguides potentially lend themselves to the implementation of high performance nanophotonic components, and open up promising opportunities for a variety of intriguing applications on the nanoscale.
TL;DR: In this article, a low-cost Silicon-on-Glass (SOG) integrated circuit technology is proposed for millimeter-wave (mmW) applications, for the first time.
Abstract: A low-cost Silicon-on-Glass (SOG) integrated circuit technology is proposed for millimeter-wave (mmW) applications, for the first time. In the proposed technology, all mmW passive components are made of high-resistivity Silicon (Si) on a glass substrate. The proposed technique leads to a high-precision and low-cost fabrication process, which eliminates the need for costly assembly of the complex structures. This is achieved by photolithography and dry etching of the entire integrated passive circuit through the Si layer of the SOG wafer. Silicon-on-Glass dielectric waveguide, as the basic component of the SOG integrated circuit, is theoretically and experimentally investigated. A test setup is designed to measure propagation characteristics of the proposed SOG waveguide. Measured dispersion diagrams of the SOG dielectric waveguide show average attenuation constants of 0.63 dB/cm, 0.28 dB/cm, and 0.53 dB/cm over 55–65 GHz, 90–110 GHz, and 140–170 GHz, respectively.
TL;DR: In this article, a hetero-junction fully depleted (FD) tunnel field effect transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed.
TL;DR: The mode property and light propagation in a tapered silicon-on-insulator (SOI) nanowire with angled sidewalls is analyzed and mode hybridization is observed and mode conversion between the TM fundamental mode and higher-order TE modes happens.
Abstract: The mode property and light propagation in a tapered silicon-on-insulator (SOI) nanowire with angled sidewalls is analyzed. Mode hybridization is observed and mode conversion between the TM fundamental mode and higher-order TE modes happens when light propagates in a waveguide taper which is used very often in the design of photonic integrated devices. This mode conversion ratio is possible to be very high (even close to 100%) when the taper is long enough to be adiabatic, which might be useful for some applications of multimode photonics. When the mode conversion is undesired to avoid any excess loss as well as crosstalk for photonic integrated circuits, one can depress the mode conversion by compensating the vertical asymmetry in the way of reducing the sidewall angle or introducing an optimal refractive index for the upper-cladding. It is also possible to eliminate the undesired mode conversion almost and improve the desired mode conversion greatly by introducing an abrupt junction connecting two sections with different widths to jump over the mode hybridization region.
TL;DR: A short-wavelength hybrid-Cavity vertical-cavity surface-emitting laser (VCSEL) heterogeneously integrated on silicon is demonstrated, creating a cavity with the standing-wave optical field extending over the silicon- and GaAs-based parts of the cavity.
Abstract: We demonstrate a short-wavelength hybrid-cavity vertical-cavity surface-emitting laser (VCSEL) heterogeneously integrated on silicon. A GaAs-based “half-VCSEL” has been attached to a dielectric distributed Bragg reflector (DBR) on a silicon wafer using ultra-thin divinylsiloxane-bis-benzocyclobutene (DVS-BCB) adhesive bonding, thereby creating a cavity with the standing-wave optical field extending over the silicon- and GaAs-based parts of the cavity. A 9 µm oxide aperture diameter VCSEL with a threshold current of 1.2 mA produces 1.6 mW optical output power at 6.0 mA bias current with a wavelength of ~845 nm.
TL;DR: The first implementation of a single-photon avalanche diode in standard silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology is reported, which exhibits a timing response without exponential tail and provides a remarkable timing jitter of 65 ps (FWHM).
Abstract: This paper reports on the first implementation of a single-photon avalanche diode (SPAD) in standard silicon on insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The SPAD is realized in a circular shape, and it is based on a P+/N-well junction along with a P-well guard-ring structure formed by lateral diffusion of two closely spaced N-well regions. The SPAD electric-field profile is analyzed by means of simulation to predict the breakdown voltage and the effectiveness of premature edge breakdown. Measurements confirm these predictions and also provide a complete characterization of the device, including current-voltage characteristics, dark count rate (DCR), photon detection probability (PDP), afterpulsing probability, and photon timing jitter. The SOI CMOS SPAD has a PDP above 25% at 490-nm wavelength and, thanks to built-in optical sensitivity enhancement mechanisms, it is as high as 7.7% at 850-nm wavelength. The DCR is 244 Hz/μm2, and the afterpulsing probability is less than 0.1% for a dead time longer than 200 ns. The SPAD exhibits a timing response without exponential tail and provides a remarkable timing jitter of 65 ps (FWHM). The new device is well suited to operate in backside illumination within complex three-dimensional (3D) integrated circuits, thus contributing to a great improvement of fill factor and jitter uniformity in large arrays.
TL;DR: A 1×4 silicon-on-insulator demultiplexer exhibiting a significant reduction of its thermo-optical sensitivity in the O-band is reported on, with promising performances for both the crosstalk and the insertion losses.
Abstract: We report on the design, fabrication, and characterization of a 1×4 silicon-on-insulator (SOI) demultiplexer exhibiting a significant reduction of its thermo-optical sensitivity in the O-band. The optical filtering is achieved by cascading several Mach–Zehnder interferometers (MZIs) fabricated on a 300-nm-thick SOI platform. Owing to an asymmetric design of the confinement for each MZIs, we found an athermal criterium that satisfies the spectral requirements. The thermal sensitivity of the structure is analyzed by a semi-analytical model in order to create an athermal multiplexer. Fiber-to-fiber thermo-optical testing reveals a thermal sensitivity of around 17 pm/°C reduced by 75% compared to the standard devices with promising performances for both the crosstalk (15 dB), the insertion losses (4 dB), and absolute lambda registration (<0.25 nm).
TL;DR: In this article, the authors present the design and implementation of phononic crystals (PnCs) in the back-end-of-line (BEOL) of commercial CMOS technologies with bandgaps in the gigahertz frequencies to be used for enhanced acoustical confinement in CMOS-RBTs.
Abstract: Resonant body transistors (RBTs) are solid state, actively sensed microelectromechanical systems (MEMS) resonators that can be implemented in commercial CMOS technologies. With small footprint, high- $Q$ , and scalability to gigahertz frequencies, they form basic building blocks for radio frequency (RF) front-ends and timing applications. Toward the goal of seamless CMOS integration, this paper presents the design and implementation of phononic crystals (PnCs) in the back-end-of-line (BEOL) of commercial CMOS technologies with bandgaps in the gigahertz frequencies to be used for enhanced acoustical confinement in CMOS-RBTs. Lithographically defined PnC dimensions allow for bandgap engineering, providing flexibility in resonator design, and allowing for multiple frequencies on a single chip. The theoretical basis for analyzing generic PnCs is presented, with focus on the special case of implementing PnCs in CMOS BEOL layers. The effect of CMOS process variations on the performance of such PnCs is also considered. The analysis presented in this paper establishes a methodology for assessing different CMOS technologies for the integration of unreleased CMOS-MEMS resonators. This paper also discusses the importance of uniformity of the acoustical cavity in the nonresonant dimension and its effect on overall resonator performance. A PnC implementation in IBM 32-nm silicon on insulator (SOI) BEOL layers is demonstrated to achieve 85% fractional-bandgap $\sim 4.5$ -GHz frequency. With better energy confinement, the proposed CMOS-RBTs achieve a quality factor $Q$ of 252, which corresponds to $8\times $ improvement over the previous generation RBTs, which did not include PnCs. The presented devices have a footprint of 5 $\mu \text{m}~\times7\mu \text{m}$ . This paper concludes with a discussion of the properties required of a CMOS technology for high performance RBT implementation. [2014-0364]
TL;DR: In this article, the authors proposed a PBO-PSOI structure for LDMOSFETs with periodic buried oxide layer (PBO) for enhancing breakdown voltage and self-heating effects (SHEs).
TL;DR: This work proposes simple structures for silicon-on-insulator transverse electric (TE)-pass and transverse magnetic (TM)-pass polarizers based on the resonance tunneling effect in silicon waveguides which are the shortest reported lengths to the best of the authors' knowledge.
Abstract: We investigate the polarization-dependent resonance tunneling effect in silicon waveguides to achieve ultra-compact and highly efficient polarization fitters for integrated silicon photonics, to the best of our knowledge for the first time. We hence propose simple structures for silicon-on-insulator transverse electric (TE)-pass and transverse magnetic (TM)-pass polarizers based on the resonance tunneling effect in silicon waveguides. The suggested TE-pass polarizer has insertion losses (IL), extinction ratio (ER), and return losses (RL) of 0.004 dB, 18 dB, and 24 dB, respectively; whereas, the TM-pass polarizer is characterized by IL, ER, and RL of 0.15 dB, 20 dB, and 23 dB, respectively. Both polarizers have an ultra-short device length of only 1.35 and 1.31 μm for the TE-pass and the TM-pass polarizers which are the shortest reported lengths to the best of our knowledge.
19 Mar 2015
TL;DR: A hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology is presented, promising a disruptive alternative for next-generation scalable data centers.
Abstract: Integrated photonic interconnect technology is free from the bandwidth-distance limitation that intrinsically exists in electrical interconnects, promising a disruptive alternative for next-generation scalable data centers. Silicon photonic platforms have been reported based on monolithic and hybrid integration. Monolithic systems mitigate integration overhead but require compromise in either electronic or photonic device performance [1,2]. Hybrid integration allows for independent process selection for each device so that overall system can potentially achieve the best performance [3]. This paper presents a hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology. A pseudo-differential driver with pre-emphasis enables an 800MHz bandwidth (BW) carrier-injection ring modulator to operate at 25Gb/s with power efficiency of 2.9pJ/b. A TIA implements two BW-enhancement techniques: a regulated-cascode (RGC) input stage with shunt-shunt feedback and T-coil inductive peaking, and a hybrid offset calibration, achieving 25Gb/s with power efficiency of 2.0pJ/b and a sensitivity of −8.0dBm OMA.