Showing papers on "Silicon on insulator published in 2017"

Review of Silicon Carbide Power Devices and Their Applications

Abstract: Silicon carbide (SiC) power devices have been investigated extensively in the past two decades, and there are many devices commercially available now. Owing to the intrinsic material advantages of SiC over silicon (Si), SiC power devices can operate at higher voltage, higher switching frequency, and higher temperature. This paper reviews the technology progress of SiC power devices and their emerging applications. The design challenges and future trends are summarized at the end of the paper.

Monolithic InGaAs nanowire array lasers on silicon-on-insulator operating at room temperature

Abstract: Chip-scale integrated light sources are a crucial component in a broad range of photonics applications. III–V semiconductor nanowire emitters have gained attention as a fascinating approach due to their superior material properties, extremely compact size, and capability to grow directly on lattice-mismatched silicon substrates. Although there have been remarkable advances in nanowire-based emitters, their practical applications are still in the early stages due to the difficulties in integrating nanowire emitters with photonic integrated circuits. Here, we demonstrate for the first time optically pumped III–V nanowire array lasers monolithically integrated on silicon-on-insulator (SOI) platform. Selective-area growth of InGaAs/InGaP core/shell nanowires on an SOI substrate enables the nanowire array to form a photonic crystal nanobeam cavity with superior optical and structural properties, resulting in the laser to operate at room temperature. We also show that the nanowire array lasers are effectively c...

200 V Enhancement-Mode p-GaN HEMTs Fabricated on 200 mm GaN-on-SOI With Trench Isolation for Monolithic Integration

Abstract: Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size

Fourier transform spectrometer on silicon with thermo-optic non-linearity and dispersion correction

Abstract: The integration of miniaturized optical spectrometers into mobile platforms will have an unprecedented impact on applications ranging from unmanned aerial vehicles (UAVs) to mobile phones. To address this demand, silicon photonics stands out as a platform capable of delivering compact and cost-effective devices. The Fourier transform spectrometer (FTS) is largely used in free-space spectroscopy, and its implementation in silicon photonics will contribute to bringing broadband operation and fine resolution to the chip scale. The implementation of an integrated silicon photonics FTS (Si-FTS) must nonetheless take into account effects such as waveguide dispersion and non-linearity of refractive index tuning mechanisms. Here we present the modeling and experimental demonstration of a silicon-on-insulator (SOI) Si-FTS with integrated microheaters. We show how the power spectral density (PSD) of a light source and the interferogram measured with the Si-FTS can be related through a simple Fourier transform (FT), provided the optical frequency and time delay are corrected to account for dispersion, thermo-optic non-linearity and thermal expansion. We calibrate the Si-FTS, including the correction parameters, using a tunable laser source and we successfully retrieve the PSD of a broadband source. The aforementioned effects are shown to effectively enhance the Si-FTS resolution when properly accounted for. Finally, we discuss the Si-FTS resilience to chip-scale fabrication variations, a major advantage for large-scale manufacturing. Providing design flexibility and robustness, the Si-FTS is poised to become a fundamental building-block for on-chip spectroscopy

Optimized sensitivity of Silicon-on-Insulator (SOI) strip waveguide resonator sensor.

Abstract: Evanescent field sensors have shown promise for biological sensing applications. In particular, Silicon-on-Insulator (SOI)-nano-photonic based resonator sensors have many advantages for lab-on-chip diagnostics, including high sensitivity for molecular detection and compatibility with CMOS foundries for high volume manufacturing. We have investigated the optimum design parameters within the fabrication constraints of Multi-Project Wafer (MPW) foundries that result in the highest sensitivity for a resonator sensor. We have demonstrated the optimum waveguide thickness needed to achieve the maximum bulk sensitivity with SOI-based resonator sensors to be 165 nm using the quasi-TM guided mode. The closest thickness offered by MPW foundry services is 150 nm. Therefore, resonators with 150 nm thick silicon waveguides were fabricated resulting in sensitivities as high as 270 nm/RIU, whereas a similar resonator sensor with a 220 nm thick waveguide demonstrated sensitivities of approximately 200 nm/RIU.

L-shaped fiber-chip grating couplers with high directionality and low reflectivity fabricated with deep-UV lithography

Abstract: Grating couplers enable position-friendly interfacing of silicon chips by optical fibers. The conventional coupler designs call upon comparatively complex architectures to afford efficient light coupling to sub-micron silicon-on-insulator (SOI) waveguides. Conversely, the blazing effect in double-etched gratings provides high coupling efficiency with reduced fabrication intricacy. In this Letter, we demonstrate for the first time, to the best of our knowledge, the realization of an ultra-directional L-shaped grating coupler, seamlessly fabricated by using 193 nm deep-ultraviolet (deep-UV) lithography. We also include a subwavelength index engineered waveguide-to-grating transition that provides an eight-fold reduction of the grating reflectivity, down to 1% (−20 dB). A measured coupling efficiency of −2.7 dB (54%) is achieved, with a bandwidth of 62 nm. These results open promising prospects for the implementation of efficient, robust, and cost-effective coupling interfaces for sub-micrometric SOI waveguides, as desired for large-volume applications in silicon photonics.

Demonstration of AlN Schottky Barrier Diodes With Blocking Voltage Over 1 kV

Abstract: This letter reports the first demonstration of 1-kV-class AlN Schottky barrier diodes on sapphire substrates by metal organic chemical vapor deposition. The device structure mimics the silicon-on-insulator (SOI) technology, consisting of thin $n$ -AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the devices show outstanding performances with a low turn-ON voltage of 1.2 V, a high ON/OFF ratio of $\sim 10^{5}$ , a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. The devices also exhibit excellent thermal stability over 500 K owing to the ultra-wide bandgap of AlN. The breakdown voltage of the devices can be further improved by employing field plate, edge termination technologies, and optimizing the SOI-like device structure. This letter presents a cost-effective route to high performance AlN-based Schottky barrier diodes for high-power, high-voltage, and high-temperature applications.

Broadband Silicon-On-Insulator directional couplers using a combination of straight and curved waveguide sections

Abstract: Broadband Silicon-On-Insulator (SOI) directional couplers are designed based on a combination of curved and straight coupled waveguide sections. A design methodology based on the transfer matrix method (TMM) is used to determine the required coupler section lengths, radii, and waveguide cross-sections. A 50/50 power splitter with a measured bandwidth of 88 nm is designed and fabricated, with a device footprint of 20 μm × 3 μm. In addition, a balanced Mach-Zehnder interferometer is fabricated showing an extinction ratio of >16 dB over 100 nm of bandwidth.

Operation of high-speed silicon photonic micro-disk modulators at cryogenic temperatures

Abstract: Significant progress has been made in the field of silicon photonics over the past two decades. Silicon photonics provides substantial performance advantages in many data processing and transfer applications. Until now, the benefits of active silicon photonics in cryogenic systems have remained unexplored. Here we demonstrate the operation of a high-speed, CMOS compatible silicon micro-disk modulator transmitting data at rates up to 10 Gb/s and at temperatures down to 4.8 K. This opens the door for the use of silicon photonics as an interface to low temperature, bandwidth intensive systems such as high-performance superconducting-based computing and integrated quantum optics circuits interfacing to superconducting single-photon detectors.

Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration

Abstract: The race on the Complementary Metal-Oxide-Semiconductor (CMOS) More Moore integration scale has brought to light several major limitations for efficient planar process integration starting with the 40 nm technology node. The transistor channel was more and more difficult to control in terms of electrostatics, and many process engineering methods (such as, for example, Silicon strain) were used to provide transistors with good carrier speed and decent electrical characteristics. Starting from the 28-nm node, the obvious solution for transistors with increased electrical performances was the use of fully depleted devices. Two integration methods have been identified by the semiconductor industry for these fully depleted devices: Fully Depleted Silicon on Insulator (FD-SOI) CMOS and Fin-FET CMOS devices. While the fundamental carrier semiconductor equations are similar, the process integration is very different. This article focuses on planar FDSOI CMOS technology features as integrated by STMicroelectronics in the 28-nm node [1], [2], and its specificities for analog, radio frequency (RF), millimeter wave (mmW), and mixed signal systemon-chip (SoC) integration.

Analytical Model of pH sensing Characteristics of Junctionless Silicon on Insulator ISFET

Abstract: In this paper, an analytical model has been developed for junctionless silicon on insulator ion-sensitive FET for pH sensing applications. The pH sensors detect the change of the hydrogen ion concentration in the aqueous solution. The modeled results show good agreement with the simulation results obtained by using Sentaurus. The electrolyte region has been considered by changing appropriate intrinsic semiconductor material in which the electron and hole charges represent the mobile ions in the aqueous solution. The effect of pH on surface potential, threshold voltage, and drain current has been investigated through model and simulations. In addition, the impact of different gate oxide materials, which act as adhesion layer, has been investigated. The pH response is defined as the amount of threshold voltage shift when the pH (in the injected solution) is varied from lower to higher values. Effect of the electrolyte region thickness on the pH sensitivity has also been discussed in this paper.

Fabrication of Novel MEMS Microgrippers by Deep Reactive Ion Etching With Metal Hard Mask

Abstract: The fabrication of a novel class of microgrippers is demonstrated by means of bulk microelectromechanical systems (MEMS) technology using silicon on insulator wafer substrates and deep reactive ion etching. Hard masking is implemented to maximize the selectivity of the bulk etching using sputtered aluminum and aluminum–titanium thin films. The micro-roughness problem related to the use of metal mask is addressed by testing different mask combinations and etching parameters. The O2 flow, SF6 pressure, wafer temperature, and bias power are examined, and the effect of each parameter on micro-masking is assessed. Sidewall damage associated with the use of a metal mask is eliminated by interposing a dielectric layer between silicon substrate and metal mask. Dedicated comb-drive anchors are implemented to etch safely both silicon sides down to the buried oxide, and to preserve the wafer integrity until the final wet release of the completed structures. A first set of complete devices is realized and tested under electrical actuation. [2017-0039]

Compact, submilliwatt, 2 × 2 silicon thermo-optic switch based on photonic crystal nanobeam cavities

Abstract: We propose and experimentally demonstrate a 2×2 thermo-optic (TO) crossbar switch implemented by dual photonic crystal nanobeam (PCN) cavities within a silicon-on-insulator (SOI) platform. By thermally tuning the refractive index of silicon, the resonance wavelength of the PCN cavities can be red-shifted. With the help of the ultrasmall mode volumes of the PCN cavities, only ∼0.16 mW power is needed to change the switching state. With a spectral passband of 0.09 nm at the 1583.75 nm operation wavelength, the insertion loss (IL) and crosstalk (CT) performances were measured as IL(bar)=−0.2 dB, CT(bar)=−15 dB, IL(cross)=−1.5 dB, and CT(cross)=−15 dB. Furthermore, the thermal tuning efficiency of the fabricated device is as high as 1.23 nm/mW.

Telecom-Wavelength Bottom-up Nanobeam Lasers on Silicon-on-Insulator

Abstract: Semiconductor nanowire lasers are considered promising ultracompact and energy-efficient light sources in the field of nanophotonics. Although the integration of nanowire lasers onto silicon photonic platforms is an innovative path toward chip-scale optical communications and photonic integrated circuits, operating nanowire lasers at telecom-wavelengths remains challenging. Here, we report on InGaAs nanowire array lasers on a silicon-on-insulator platform operating up to 1440 nm at room temperature. Bottom-up photonic crystal nanobeam cavities are formed by growing nanowires as ordered arrays using selective-area epitaxy, and single-mode lasing by optical pumping is demonstrated. We also show that arrays of nanobeam lasers with individually tunable wavelengths can be integrated on a single chip by the simple adjustment of the lithographically defined growth pattern. These results exemplify a practical approach toward nanowire lasers for silicon photonics.

Design Space Exploration of Hysteresis-Free HfZrO x -Based Negative Capacitance FETs

Abstract: In this letter, we investigate the design space of hysteresis-free negative capacitance FETs (NCFETs) by performing a cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully depleted SOI-FETs, and sub-10-nm FinFETs. Our simulation analysis shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control, which enables better capacitance matching with the ferroelectric. A low-voltage NC-FinFET operating down to 0.25 V is predicted using ultra-thin 3-nm FE-HZO.

Realization of an ultra-compact polarization beam splitter using asymmetric MMI based on silicon nitride / silicon-on-insulator platform.

Abstract: We have experimentally demonstrated a compact polarization beam splitter (PBS) based on the silicon nitride/silicon-on-insulator platform using the recently proposed augmented-low-index-guiding (ALIG) waveguide structure. The two orthogonal polarizations are split in an asymmetric multimode interference (MMI) section, which was 1.6 μm wide and 4.8 μm long. The device works well over the entire C-band wavelength range and has a measured low insertion loss of less than 1 dB. The polarization extinction ratio at the Bar Port is approximately 17 dB and at the Cross Port is approximately 25 dB. The design of the device is robust and has a good fabrication tolerance.

Nanopillar quantum well lasers directly grown on silicon and emitting at silicon-transparent wavelengths

Abstract: Future expansion of computing capabilities relies on a reduction of energy consumption in silicon-based integrated circuits. A promising solution is to replace electrical wires with optical connections, for which a key component is a nanolaser that coherently emits into silicon-based waveguides to route information across a chip, in place of bulky off-chip devices. We report room temperature, sub-μm2 footprint, quantum-well-in-nanopillar lasers grown directly on silicon and silicon-on-insulator (SOI) substrates that emit within the silicon-transparent wavelength range under optical excitation. The laser wavelength is controlled by changing the InGaAs quantum well thickness and alloy composition, quite independent of lattice mismatch with the InP barrier, a unique property of the 3D core-shell growth mode. We achieve excellent luminescence yield and low continuous wave transparency power due to the well-passivated InGaAs/InP interfaces. These sub-μm2 footprint long-wavelength lasers could enable optoelectronic integration and photon routing with silicon waveguides on the technologically relevant SOI platform.

Compact polarization beam splitter for silicon photonic integrated circuits with a 340-nm-thick silicon core layer

Abstract: A polarization beam splitter (PBS) is proposed and realized for silicon photonic integrated circuits with a 340-nm-thick silicon core layer by introducing an asymmetric directional coupler (ADC), which consists of a silicon-on-insulator (SOI) nanowire and a subwavelength grating (SWG) waveguide. The SWG is introduced to provide an optical waveguide which has much higher birefringence than a regular 340-nm-thick SOI nanowire, so that it is possible to make the phase-matching condition satisfied for TE polarization only in the present design when the waveguide dimensions are optimized. Meanwhile, there is a significant phase mismatching for TM polarization automatically. In this way, the present ADC enables strong polarization selectivity to realize a PBS that separates TE and TM polarizations to the cross and through ports, respectively. The realized PBS has a length of ∼2 μm for the coupling region. For the fabricated PBS, the extinction ratio (ER) is 15–30 dB and the excess loss is 0.2–2.6 dB for TE polarization while the ER is 20–27 dB and the excess loss is 0.3–2.8 dB for TM polarization when operating in the wavelength range of 1520–1580 nm.

Compact and low loss 90° optical hybrid on a silicon-on-insulator platform

Abstract: We present a compact and low loss 90° optical hybrid on a silicon-on-insulator (SOI) platform for coherent receiving systems. Our 90° optical hybrid uses a novel topology, comprising one Y-junction and three 2x2 multimode interference (MMI) couplers. The geometry of the 90° optical hybrid is fully optimized using particle swarm optimization (PSO). The fabricated 90° optical hybrid has a compact footprint of 21.6 μm x 27.9 μm, with an insertion loss less than 0.5 dB, a common mode rejection ratio (CMRR) larger than 30 dB, and phase error smaller than 3° in the C-band across 22 reticles on one wafer. The measured phase error (< 3°) in a packaged coherent receiver further confirms the excellent performance of the 90° optical hybrid.

Monolithically-Integrated TE-mode 1D Silicon-on-Insulator Isolators using Seedlayer-Free Garnet.

Abstract: The first experimental TE-mode silicon-on-insulator (SOI) isolators using Faraday Rotation are here realized to fill the ‘missing link’ in source-integrated near infrared photonic circuits. The isolators are simple 1D 2-element waveguides, where garnet claddings and longitudinal magnetic fields produce nonreciprocal mode conversion, the waveguide equivalent of Faraday Rotation (FR). Quasi-phase matched claddings are used to overcome the limitations of birefringence. Current experimental SOI isolators use nonreciprocal phase shift (NRPS) in interferometers or ring resonators, but to date NRPS requires TM-modes, so the TE-modes normally produced by integrated lasers cannot be isolated without many ancillary polarisation controls. The presented FR isolators are made via lithography and sputter deposition, which allows facile upscaling compared to the pulsed laser deposition or wafer bonding used in the fabrication of NRPS devices. Here, isolation ratios and losses of 11 dB and 4 dB were obtained, and future designs are identified capable of isolation ratios >30 dB with losses <6 dB.

Physics and performance of nanoscale semiconductor devices at cryogenic temperatures

Abstract: The physics and performance of various advanced semiconductor devices, which are the most promising for the end of the ITRS roadmap, are investigated in a wide temperature range down to 20 K. The transport parameters in front and/or back channels in fully depleted ultrathin film SOI devices, Trigate, FinFET, Omega-gate nanowire FET and 3D-stacked SiGe nanowire FETs, fabricated with high-k dielectrics/metal gate, elevated source/drain, different channel orientations, shapes and strains, are addressed. The impacts of the gate length, Si film and wire diameter down to 10 nm, are also shown. The variations of the phonon, Coulomb, neutral defects and surface roughness scattering as a function of temperature and device architecture are highlighted. An overview of the influence of temperature on other main electrical parameters of MOSFETs, nanowires FETs and tunnel FETs, such as threshold voltage, subthreshold swing, leakage and driving currents is also given.

Dispersion control of silicon nanophotonic waveguides using sub-wavelength grating metamaterials in near- and mid-IR wavelengths.

Abstract: Controlling the group velocity dispersion of silicon nanophotonic waveguides has been recognized as a key ingredient to enhance the development of various on-chip optical applications. However, the strong wavelength dependence of the dispersion in waveguides implemented on the high index contrast silicon-on-insulator (SOI) platform substantially hinders their wideband operation, which in turn, limits their deployment. In this work, we exploit the potential of non-resonant sub-wavelength grating (SWG) nanostructures to perform a flexible and wideband control of dispersion in SOI waveguides. In particular, we demonstrated that the overall dispersion of the SWG-engineered metamaterial waveguides can be tailored across the transparency window of the SOI platform, keeping easy-to-handle single-etch step manufacturing. The SWG silicon waveguides overcladded by silicon nitride exhibit significant reduction of wavelength dependence of dispersion, yet providing intriguing and customizable synthesis of various attractive dispersion profiles. These include large normal up to low anomalous operation regimes, both of which could make a great promise for plethora of emerging applications in silicon photonics.

Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

Optical pump-rejection filter based on silicon sub-wavelength engineered photonic structures.

Abstract: The high index contrast of the silicon-on-insulator (SOI) platform allows the realization of ultra-compact photonic circuits. However, this high contrast hinders the implementation of narrow-band Bragg filters. These typically require corrugation widths of a few nanometers or double-etch geometries, hampering device fabrication. Here we report, for the first time, to the best of our knowledge, on the realization of SOI Bragg filters based on sub-wavelength index engineering in a differential corrugation width configuration. The proposed double periodicity structure allows narrow-band rejection with a single etch step and relaxed width constraints. Based on this concept, we experimentally demonstrate a single-etch, 220 nm thick, Si Bragg filter featuring a corrugation width of 150 nm, a rejection bandwidth of 1.1 nm, and an extinction ratio exceeding 40 dB. This represents a 10-fold width increase, compared to conventional single-periodicity, single-etch counterparts with similar bandwidths.

Comparison of SOI Versus Bulk FinFET Technologies for 6T-SRAM Voltage Scaling at the 7-/8-nm Node

Abstract: The electrostatic benefit of using a silicon-on-insulator (SOI) wafer substrate versus a bulk-silicon wafer substrate with optimized supersteep retrograde (SSR) doping for a low-power 7-/8-nm FinFET technology is investigated via 3-D device simulations and a fitted compact model to estimate the manufacturing yield of six-transistor SRAM cells. SOI FinFET technology is projected to provide only slight improvement in performance and minimum cell operating voltage as compared with SSR FinFET technology.

Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents

Abstract: In this paper, a technology for top-down single-gated Schottky barrier transistor is presented exhibiting the highest symmetry of on-currents for n- and p-conductance of such silicon-on-insulator-based devices. The symmetry in the current-voltage-characteristics is a mandatory requirement to realize circuits with reconfigurable nanowire field effect transistors (RFETs) whose channel can be switched electrostatically between n- and p-conductance. It was achieved by an oxidation-induced stressor layer covering the nanowire. Together with the demand for only a single gate potential level, this opens the route to build top-down RFET circuits. Our device features an atomically sharp Schottky junction between intruded nickel silicide and the intrinsic nanowire channel.

A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure.

Abstract: This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e-rms, low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

Al transmon qubits on silicon-on-insulator for quantum device integration

Abstract: We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T_1 = 3.5 μs and T_2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

Abstract: In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530–1565 nm) with excess loss better than 0.23 dB.