Showing papers on "Silicon on insulator published in 2019"

Optimization of thermo-optic phase-shifter design and mitigation of thermal crosstalk on the SOI platform.

Abstract: We first optimize the design and compare the performance of thermo-optic phase-shifters based on TiN metal and N++ doped silicon, in the same SOI process. The designs don’t require special material processing, show negligible loss, and have very stable power consumption. The optimum TiN design has a switching powerPπ=21.4 mW and a time constantτ=5.6 µs, whereasPπ=22.8 mW andτ=2.2 µs for the best N++ Si design, enabling 2.5x faster switching compared to the metal heater. Doped-Si-based heaters are therefore the most practical and efficient on standard SOI. In addition, to optimize the layout density of highly integrated dies, we experimentally characterize internal and external thermal crosstalk for tunable Mach-Zehnder interferometers (MZIs) based on both heater designs for various power, distances, and etching patterns. Deep trenches are the best structures not involving special fabrication techniques to mitigate heat leakage affecting phase-sensitive devices close to heaters. Given the numerous applications of thermal tuners, this work is relevant to almost all silicon photonics designers.

Low-Insertion-Loss and Power-Efficient 32 × 32 Silicon Photonics Switch With Extremely High-Δ Silica PLC Connector

Abstract: We fabricate a 32 × 32 silicon photonics switch on a 300-mm silicon-on-insulator wafer by using our complementary metal-oxide-semiconductor pilot line equipped with an immersion ArF scanner and demonstrate an average fiber-to-fiber insertion loss of 10.8 dB with a standard deviation of 0.54 dB, and on-chip electric power consumption of 1.9 W. The insertion loss and the power consumption are approximately 1/60, and less than 1/4 of our previous results, respectively. These significant improvements are achieved by design and fabrication optimization of waveguides and intersections on the chip, and by employing a novel optical fiber connector based on extremely-high-Δ silica planar-lightwave-circuit (PLC) technology. The minimum crosstalk was −26.6 dB at a wavelength of 1547 nm, and −20-dB crosstalk bandwidth was 3.5 nm. Furthermore, we demonstrate low-crosstalk bandwidth expansion by using output port exchanged element switches. We achieve a −20 dB crosstalk bandwidth of 14.2 nm, which is four-times wider than that of the conventional element switch based 32 × 32 switch.

Telecom InP/InGaAs nanolaser array directly grown on (001) silicon-on-insulator

Abstract: A compact, efficient, and monolithically grown III–V laser source provides an attractive alternative to bonding off-chip lasers for Si photonics research. Although recent demonstrations of microlasers on (001) Si wafers using thick metamorphic buffers are encouraging, scaling down the laser footprint to nanoscale and operating the nanolasers at telecom wavelengths remain significant challenges. Here, we report a monolithically integrated in-plane InP/InGaAs nanolaser array on (001) silicon-on-insulator (SOI) platforms with emission wavelengths covering the entire C band (1.55 μm). Multiple InGaAs quantum wells are embedded in high-quality InP nanoridges by selective-area growth on patterned (001) SOI. Combined with air-cladded InP/Si optical cavities, room-temperature operation at multiple telecom bands is obtained by defining different cavity lengths with lithography. The demonstration of telecom-wavelength monolithic nanolasers on (001) SOI platforms presents an important step towards fully integrated Si photonics circuits.

Broadband, low-loss silicon photonic Y-junction with an arbitrary power splitting ratio.

Abstract: Photonic integrated circuits (PICs) often require broadband power splitters such as Y-junctions for signal monitoring, signal feedback, power distribution, etc., with various splitting ratios. Therefore, a parameterized Y-junction with an arbitrary power splitting ratio that can be selected in layout design is desired in a PIC library. Here, we propose an ultra-compact (1.4 μm × 2.3 μm) Y-junction on the 220-nm-thick silicon-on-insulator (SOI) platform for an arbitrary splitting ratio with a programmable design. It applies smooth curvatures for a good tolerance to fabrication errors. Rigorous 3D-FDTD simulations predict an excess loss below 0.36 dB and a splitting-ratio variation of less than 1 dB over 100 nm. Experimental results achieved using a CMOS-compatible silicon photonics process show an excess loss of lower than 0.5 dB for a splitting ratio varied from 0 to −18 dB across the entire C band. Both numerical and experimental results show that the power splitting ratio of the proposed device is weakly wavelength dependent.

Surface acoustic wave photonic devices in silicon on insulator.

Abstract: Opto-mechanical interactions in planar photonic integrated circuits draw great interest in basic research and applications. However, opto-mechanics is practically absent in the most technologically significant photonics platform: silicon on insulator. Previous demonstrations required the under-etching and suspension of silicon structures. Here we present surface acoustic wave-photonic devices in silicon on insulator, up to 8 GHz frequency. Surface waves are launched through absorption of modulated pump light in metallic gratings and thermo-elastic expansion. The surface waves are detected through photo-elastic modulation of an optical probe in standard race-track resonators. Devices do not involve piezo-electric actuation, suspension of waveguides or hybrid material integration. Wavelength conversion of incident microwave signals and acoustic true time delays up to 40 ns are demonstrated on-chip. Lastly, discrete-time microwave-photonic filters with up to six taps and 20 MHz-wide passbands are realized using acoustic delays. The concept is suitable for integrated microwave-photonics signal processing. The authors implement surface acoustic waves on the silicon photonics platform by exciting a metallic grating with modulated pump light to enable microwave-photonic devices without the need for piezo-electric actuation, complex suspensions or hybrid materials.

Broadband mid-infrared supercontinuum generation in dispersion-engineered silicon-on-insulator waveguide

Abstract: In this paper, we numerically investigate near- and mid-infrared supercontinuum (SC) generation in dispersion-engineered silicon-on-insulator (SOI) waveguides employing a novel side-slotted core structure. The effect of waveguide parameters on the dispersion is studied to achieve optimum dispersion profiles for SC generation in the anomalous and normal dispersion regimes. Numerical results show that by applying an input pump pulse with 200 fs width and 400 W peak power at 2.1 μm wavelength in a 10-mm-long SOI waveguide, SC spectra as wide as 2.8 μm and 2.0 μm can be obtained in the anomalous and normal dispersion regimes, respectively. These waveguides are useful as compact on-chip silicon photonic sources for spectroscopic applications in mid-infrared wavelengths.

Sub-wavelength grating-assisted polarization splitter-rotators for silicon-on-insulator platforms.

Abstract: We propose and demonstrate broadband, entirely mode-evolution-based, polarization splitter-rotators (PSR) using sub-wavelength grating (SWG) assisted adiabatic waveguides for two SOI platforms. Our PSRs are more compact than previously demonstrated entirely mode-evolution-based designs. The devices were fabricated using two fabrication processes and, in both cases, the measured spectra show close matches to the simulation results. One of the processes uses standard optical lithography and, hence, this is the first time that an SWG-based PSR has been experimentally implemented using such a process. Finally, measurements for arbitrary input polarizations on an active, automated polarization receiver, that uses one of our PSRs, are also presented.

Electrically Injected GeSn Vertical-Cavity Surface Emitters on Silicon-on-Insulator Platforms

Abstract: An efficient electrically injected group-IV light source compatible with the complementary metal-oxide-semiconductor (CMOS) process is the holy grail for realizing functional, intelligent electronic-photonic integrated circuits for a wide range of applications. The group-IV GeSn material is considered as a promising solution for efficient light sources because its bandgap can be fundamentally transformed from indirect to direct with appropriate Sn compositions. However, an important challenge in realizing efficient electrically injected light emitters is the incorporation of an optical cavity with electrical structures. Here we demonstrate, to the best of our knowledge, the first electrically injected GeSn vertical-cavity surface emitter on the silicon-on-insulator platform. A vertical cavity employing a buried oxide layer and a deposited SiO2 top layer as reflectors is developed for enhancing the electroluminescence in the GeSn active layer. Room-temperature electroluminescence experiments reveal clear c...

High-Efficiency Ultra-Broadband Multi-Tip Edge Couplers for Integration of Distributed Feedback Laser With Silicon-on-Insulator Waveguide

Abstract: A high-efficiency ultra-broadband multi-tip edge coupler based on a silicon-on-insulator platform for direct coupling with the elliptic beam of a distributed feedback laser was developed. The device is composed of a multi-tip section and a combiner section with extra offset regions to reduce the mode mismatch caused by the structural discontinuity which results from a limitation of the fabrication process that creates an inevitable gap width at the junction between the two sections. The widths and the spacing of the tips for the multi-tip section and the extra offset region for the combiner section are fine-tuned by using the particle swarm optimization method to reduce the mode mismatch. A high overall coupling efficiency up to 90.68% (0.4249 dB) at 1550 nm can be achieved for the optimized 90-μm-long four-tip edge coupler. The device can be operated over a broad spectral range of 1260–1675 nm with less than 1 dB extra loss. With its high-efficiency ultra-broadband operation and small device footprint, the proposed device is promising for laser-to-chip edge coupling in silicon photonics.

Steep Slope Silicon-On-Insulator Feedback Field-Effect Transistor: Design and Performance Analysis

Abstract: Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail.

High-speed waveguide integrated silicon photodetector on a SiN-SOI platform for short reach datacom

Abstract: We present a waveguide integrated high-speed Si photodetector integrated with a silicon nitride (SiN) waveguide on an silicon-on-insulator (SOI) platform for short reach data communication in a 850 nm wavelength band. We demonstrate a waveguide couple Si pin photodetector responsivity of 0.44 A/W at 25 V bias. The frequency response of the photodetector is evaluated by the coupling of a femtosecond laser source through an SiN grating coupler of the integrated photodetector. We estimate a 3 dB bandwidth of 14 GHz at 20 V bias which, to the best of our knowledge, is the highest reported bandwidth for a waveguide integrated Si photodetector. We also present detailed optoelectronic DC and AC characterization of the fabricated devices. The demonstrated integrated photodetector could enable an integrated solution for scaling of short reach data communication and connectivity.

High-speed double layer graphene electro-absorption modulator on SOI waveguide.

Abstract: We report on a C-band double layer graphene electro-absorption modulator on a passive SOI platform showing 29GHz 3dB-bandwith and NRZ eye-diagrams extinction ratios ranging from 17 dB at 10 Gb/s to 13 dB at 50 Gb/s Such high modulation speed is achieved thanks to the quality of the CVD pre-patterned single crystal growth and transfer on wafer method that permitted the integration of high-quality scalable graphene and low contact resistance By demonstrating this high-speed CVD graphene EAM modulator integrated on Si photonics and the scalable approach, we are confident that graphene can satisfy the main requirements to be a competitive technology for photonics

Improvement in electrical characteristics of Silicon on Insulator (SOI) transistor using Graphene material

Abstract: This paper presents the electrical characteristics of a short channel Silicon on Insulator (SOI) transistor with a graphene layer. The graphene sheet is used at the bottom of the channel close to the source side and a proportionally heavily p-type retrograde doping implanted in nearly middle of the channel. To increase the gate electrostatic control over the channel we incorporated a high-K material i.e. HfO2 as the gate oxide insulator. Due to Graphene growth and Retrograde Doping in the Channel, we called this structure “GRDC-SOI” transistor. Because graphene sheet has low band gap and high mobility, we used it to increase the on-state current. Engineered p-type retrograde doping utilized for both decreasing off-state current and increasing on-state current. These dopants cause impurity scattering in the depth of the channel and deflect electron movements and decrease off-current. On the other hand, these dopants which are located almost in the middle of the channel can play the role of base in an NPN Bipolar Junction Transistor (BJT), and turn it on and exceed the on-state current. An immense comparison among our proposed device and a device similar to GRDC-SOI but without Graphene sheet (RDC-SOI) and a conventional structure shows that our proposed device has superior electrical characteristics in terms of ION/IOFF ratio, transconductance, subthreshold slope, leakage current, breakdown voltage and short channel effects like hot carriers injection and DIBL. Our analyses demonstrate that GRDC-SOI transistor can open a window for utilizing Graphene material in digital circuits and system on chip applications.

Compact thermo-optic MZI switch in silicon-on-insulator using direct carrier injection.

Abstract: In this paper we present a compact direct current injection thermo-optic switch based on a Mach-Zehnder Interferometer configuration that is suitable for autonomous vehicle applications as it has a low heating resistance value of 97 Ω, a rapid 2.16 μs switching time constant, and a Pπ of 28 mW. The device relies on multimode interference to achieve low optical insertion losses of less than 1.1 dB per device, while allowing direct current injection to heat the waveguide and achieve fast operation speeds. Furthermore, the total resistive value can be tailored as the heating elements are placed in parallel.

Process Dependence of Soft Errors Induced by Alpha Particles, Heavy Ions, and High Energy Neutrons on Flip Flops in FDSOI

Abstract: Soft-error tolerance depending on threshold voltage of transistors was evaluated by $\alpha $ -particle, heavy-ion, and neutron irradiation. Three chips were fabricated, one embeds low-threshold general-purpose (GP) transistors and the others embed high-threshold low-power (LP) transistors in a 65 nm fully depleted silicon on insulator (FDSOI) process. There were a few errors on LPDFFs (DFFs with LP transistors). Error probability (EP) of LPDFFs was 99.88% smaller than that of GPDFFs (DFFs with GP transistors) by $\alpha $ particles. Average cross sections (CSs) of LPDFFs by heavy ions were 50% smaller than those of GPDFFs. Average soft-error rates (SERs) of LPDFFs by neutrons were 68% smaller than those of GPDFFs. 3-D device simulations revealed that CSs of the LP and GP transistors are changed by fitting methods using the work function of the gate material and doping concentration of the substrate under the BOX layer. The difference is due to the number of carriers in diffusion and silicon thickness of the raised layer above drain and source terminals.

Silicon-on-insulator free-carrier injection modulators for the mid-infrared.

Abstract: Experimental demonstrations of silicon-on-insulator waveguide-based free-carrier effect modulators operating at 3.8 μm are presented. PIN diodes are used to inject carriers into the waveguides, and are configured to (a) use free-carrier electroabsorption to create a variable optical attenuator with 34 dB modulation depth and (b) use free-carrier electrorefraction with the PIN diodes acting as phase shifters in a Mach–Zehnder interferometer, achieving a VπLπ of 0.052 V·mm and a DC modulation depth of 22 dB. Modulation is demonstrated at data rates up to 125 Mbit/s.

Fabrication of a Monolithic Implantable Neural Interface from Cubic Silicon Carbide.

Abstract: One of the main issues with micron-sized intracortical neural interfaces (INIs) is their long-term reliability, with one major factor stemming from the material failure caused by the heterogeneous integration of multiple materials used to realize the implant. Single crystalline cubic silicon carbide (3C-SiC) is a semiconductor material that has been long recognized for its mechanical robustness and chemical inertness. It has the benefit of demonstrated biocompatibility, which makes it a promising candidate for chronically-stable, implantable INIs. Here, we report on the fabrication and initial electrochemical characterization of a nearly monolithic, Michigan-style 3C-SiC microelectrode array (MEA) probe. The probe consists of a single 5 mm-long shank with 16 electrode sites. An ~8 µm-thick p-type 3C-SiC epilayer was grown on a silicon-on-insulator (SOI) wafer, which was followed by a ~2 µm-thick epilayer of heavily n-type (n+) 3C-SiC in order to form conductive traces and the electrode sites. Diodes formed between the p and n+ layers provided substrate isolation between the channels. A thin layer of amorphous silicon carbide (a-SiC) was deposited via plasma-enhanced chemical vapor deposition (PECVD) to insulate the surface of the probe from the external environment. Forming the probes on a SOI wafer supported the ease of probe removal from the handle wafer by simple immersion in HF, thus aiding in the manufacturability of the probes. Free-standing probes and planar single-ended test microelectrodes were fabricated from the same 3C-SiC epiwafers. Cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS) were performed on test microelectrodes with an area of 491 µm2 in phosphate buffered saline (PBS) solution. The measurements showed an impedance magnitude of 165 kΩ ± 14.7 kΩ (mean ± standard deviation) at 1 kHz, anodic charge storage capacity (CSC) of 15.4 ± 1.46 mC/cm2, and a cathodic CSC of 15.2 ± 1.03 mC/cm2. Current-voltage tests were conducted to characterize the p-n diode, n-p-n junction isolation, and leakage currents. The turn-on voltage was determined to be on the order of ~1.4 V and the leakage current was less than 8 μArms. This all-SiC neural probe realizes nearly monolithic integration of device components to provide a likely neurocompatible INI that should mitigate long-term reliability issues associated with chronic implantation.

APSUNY Process Design Kit (PDKv3.0): O, C and L Band Silicon Photonics Component Libraries on 300mm Wafers

Abstract: An updated process design kit (APSUNY PDKv3.0) is introduced with verified passive and active O+C+L band silicon photonics component libraries, which includes 50Gbaud (100Gbps) capable modulators, high yield splitters and detectors on 300mm SOI wafers.

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Abstract: The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

Mode-evolution-based silicon-on-insulator 3 dB coupler using fast quasiadiabatic dynamics.

Abstract: We report a 2×2 broadband and fabrication tolerant mode-evolution-based 3 dB coupler based on silicon-on-insulator rib waveguides. The operating principle of the coupler is based on the adiabatic evolution of local eigenmodes. The key element of the device is an adiabatically tapered mode evolution region, which converts two dissimilar waveguides into two identical waveguides. Contrary to conventional designs using a linear taper function where the device adiabaticity is uneven during evolution, we use the fast quasiadiabatic approach to homogenize the adiabaticity of the device, leading to a shortcut to adiabaticity. Devices with an optimized taper region of 26.3 μm are designed and fabricated in a complementary metal-oxide-semiconductor compatible process with 193 nm deep ultraviolet lithography. The measured devices exhibit a broadband 3 dB±0.5 dB splitting within a bandwidth of 100 nm, uniformly across a 200-mm wafer, showing good tolerance against fabrication variations.

Compact and Low Crosstalk Echelle Grating Demultiplexer on Silicon-On-Insulator Technology

Abstract: We report on the design of an ultra-compact integrated wavelength demultiplexer in echelle configuration for the optical O-band realized on silicon-on-insulator technology. The device has four channels with channel spacing of 800 GHz and a small footprint of 260 × 83 μm2. Channel crosstalk lower than −28 dB across the four channels is experimentally demonstrated along with insertion losses of −1.5 dB.

Novel adiabatic coupler for III-V nano-ridge laser grown on a Si photonics platform.

Abstract: While III-V lasers epitaxially grown on silicon have been demonstrated, an efficient approach for coupling them with a silicon photonics platform is still missing. In this paper, we present a novel design of an adiabatic coupler for interfacing nanometer-scale III-V lasers grown on SOI with other silicon photonics components. The starting point is a directional coupler, which achieves 100% coupling efficiency from the III-V lasing mode to the Si waveguide TE-like ground mode. To improve the robustness and manufacturability of the coupler, a linear-tapered adiabatic coupler is designed, which is less sensitive to variations and still reaches a coupling efficiency of around 98%. Nevertheless, it has a relatively large footprint and exhibits some undesired residual coupling to TM-like modes. To improve this, a more advanced adiabatic coupler whose geometry is varied along its propagation length is designed and manages to reach ∼100% coupling and decoupling within a length of 200 μm. The proposed couplers are designed for the particular case of III-V nano-ridge lasers monolithically grown using aspect-ratio-trapping (ART) together with nano-ridge engineering (NRE) but are believed to be compatible with other epitaxial III-V/Si integration platforms recently proposed. In this way, the presented coupler is expected to pave the way to integrating III-V lasers monolithically grown on SOI wafers with other photonics components, one step closer towards a fully functional silicon photonics platform.

50 μm thin Low Gain Avalanche Detectors (LGAD) for timing applications

Abstract: LGAD detectors on 300 μ m thick high resistivity p-type substrates were proposed for the first time by IMB-CNM-CSIC. They are customized Avalanche Photodiodes (APD) to obtain a high electric field region confined close to the reversed junction. Therefore, only electrons generated by an incident particle passing through the detector and drifting to the n+ contact, start the impact ionization process. Thus, the collected charge is multiplied. The basic difference between APDs and LGADs is the gain. LGADs have a moderate gain in order to avoid the inherent problems due to high multiplication: cross talk and high noise. In that way, the detector signal can be kept high without increasing the noise. These devices have been successfully fabricated and extensively characterized, before and after irradiation. Unfortunately, neutron and proton radiation cause the degradation of the gain and the creation of bulk traps, degrading the timing resolution. One way to reduce the radiation induced degradation is to minimize the substrate thickness, thus improving the timing resolution of LGAD detectors. Two technology approaches have been contemplated: the use of SOI (Silicon on insulator) substrates and Silicon to Silicon bonding substrates, both with a very thin active silicon layer of 50 μ m . As a consequence, drifting distances of generated electrons and holes are significantly reduced, resulting in a decrease in the number of electrons and holes trapped by radiation induced bulk defects. A new family of thin detectors, produced in 2 × 2 arrays prototypes, for the ATLAS experiment High Granularity Timing Detector (HGTD) is proposed. These detectors are suitable for timing applications with time resolution in the range of 30 ps at 20 °C. Optimization of the LGAD structures for the HGTD experiment and the detector experimental performances are presented and discussed.

Monolithically Integrated Reconfigurable RF MEMS Based Impedance Tuner on SOI Substrate

Abstract: This paper presents the design and implementation of a MEMS-based impedance tuner realized on a Silicon-on-Insulator (SOI) substrate. Contactless lateral MEMS varactors were realized using laterally moving capacitive thick plates whose motion was precisely controlled using Chevron actuators. The voltage required for the maximum displacement is under 12 V. These varactors are monolithically integrated with CPW lines using a single mask fabrication process on SOI substrate. The implemented MEMS capacitive varactors exhibit a capacitance range of 0.19 pf to 0.8 pf. The improvement of the Smith chart coverage is achieved by proper choice of the electrical lengths of the CPW lines and precise control of the lateral motion of the capacitive plates. The measured results demonstrate a good impedance matching coverage with an insertion loss of 2.9 dB. Details of the SOI-based fabrication process are presented along with discussions on techniques to improve the insertion loss of the device. The proposed design does not suffer from the dielectric charging, micro-welding and stiction problems associated with RF MEMS devices realized using surface micromachining processes. In addition, the device promises to be useful in high power applications, since it is constructed from lateral thick structures.

Lithium Niobate Michelson Interferometer Modulator on Silicon-On-Insulator Platform

Abstract: We propose and demonstrate a hybrid silicon and lithium niobate Michelson Interferometer Modulator (MIM) with enhanced modulation efficiency compared to a Mach-Zehnder modulator. The modulator is based on seamless integration of a high-contrast waveguide based on lithium niobate-a popular modulator material-with compact, low-loss silicon circuitry. The present device demonstrates a modulation efficiency as high as 1.2 Vcm and a low insertion loss of 3.3 dB. The 3dB electro-optic bandwidth is approximately 17.5 GHz. The optical eye diagrams, operating at 32 Gbit/s and 40 Gbit/s, with measured dynamic extinction ratios at 8 dB and 6.6 dB respectively. The present device avoids absorption loss and nonlinearity in conventional silicon modulators and demonstrates highest modulation efficiency in LN modulators, showing potential in future optical interconnects.

Selective lateral epitaxy of dislocation-free InP on silicon-on-insulator

Abstract: Efficient on-chip laser sources of Si photonics can be built from direct epitaxy of dislocation-free III–V alloys on industrial-standard (001) Si wafers. Here, we report on selective lateral epitaxy of InP on patterned (001) silicon-on-insulators (SOIs) by metal organic chemical vapor deposition. Based on the conventional “aspect ratio trapping” approach, we created undercut patterns to alter the growth front to the lateral direction. Growth of InP inside the nano-scale SOI trenches results in dislocation-free InP crystals right atop the buried oxide layer. The intimate placement of the InP crystals with the Si device layer points to the development of dislocation-free nano-ridges for integration of efficient III–V light emitters with Si-based photonic components on SOI.Efficient on-chip laser sources of Si photonics can be built from direct epitaxy of dislocation-free III–V alloys on industrial-standard (001) Si wafers. Here, we report on selective lateral epitaxy of InP on patterned (001) silicon-on-insulators (SOIs) by metal organic chemical vapor deposition. Based on the conventional “aspect ratio trapping” approach, we created undercut patterns to alter the growth front to the lateral direction. Growth of InP inside the nano-scale SOI trenches results in dislocation-free InP crystals right atop the buried oxide layer. The intimate placement of the InP crystals with the Si device layer points to the development of dislocation-free nano-ridges for integration of efficient III–V light emitters with Si-based photonic components on SOI.

General silicon-on-insulator higher-order mode converter based on substrip dielectric waveguides.

Abstract: A general silicon mode-converter waveguide that converts a fundamental mode to any higher-order mode is proposed. Specifically, dielectric substrip waveguides are inserted in the fundamental mode propagation path so that the conversion is done directly in the same propagation waveguide, without coupling the power into another waveguide as it happens in traditional mode converters. The device has a very small footprint compared to traditional converters. A mathematical model is developed to determine the design parameters of the used dielectric material and analyze the whole performance of the proposed device. Both the effective index method (EIM) and the perturbative mode-coupled theory are used in our mathematical analysis to get exact values for both the coupling coefficient and the length of the used dielectric material, so as to ensure a maximum coupled power transfer to the higher-order mode. In addition, full vectorial 3D-FDTD simulations are performed to validate our mathematical model. Our results show good agreement between the approximate EIM method and accurate full vectorial 3D-finite-difference time-domain (FDTD) simulations in characterizing the device parameters and performance. In order to validate the design model, two mode converters are simulated, fabricated, and tested for converting a fundamental TE0 mode into both first- and second-order (TE1 and TE2) modes, respectively. Good insertion losses and low crosstalks are obtained. Good agreement between simulated and fabricated results are achieved.

Room-Temperature InGaAs Nanowire Array Band-Edge Lasers on Patterned Silicon-on-Insulator Platforms

Abstract: Integration of ultracompact light sources on silicon platforms is regarded as a crucial requirement for various nanophotonic applications. In this work, InGaAs/InP core/shell nanowire array photonic crystal lasers are demon- strated on silicon-on-insulator substrates by selective-area epitaxy. 9  9 square-lattice nanowires forming photonic crystal cavities with a footprint of only 3.0  3.0 μm 2 , and a high Q factor of 23 000 are achieved by forming these nanowires on two-dimensional silicon gratings. Room-temperature lasing is observed from a fundamental band-edge mode at 1290 nm, which is the O-band of the telecommunication wavelength. Optimized growth templates and effective in-situ passivation of InGaAs nanowires enable the nanowire array to lase at a low threshold of 200 μJcm 2 , without any signature of heating or degradation above the threshold. These results represent a meaningful step toward ultracompact and monolithic III–V lasers on silicon photonic platforms

Optimization of photoluminescence from W centers in silicon-on-insulator

Abstract: W centers are trigonal defects generated by self-ion implantation in silicon that exhibit photoluminescence at 1.218 $\mu$m. We have shown previously that they can be used in waveguide-integrated all-silicon light-emitting diodes (LEDs). Here we optimize the implant energy, fluence and anneal conditions to maximize the photoluminescence intensity for W centers implanted in silicon-on-insulator, a substrate suitable for waveguide-integrated devices. After optimization, we observe near two orders of magnitude improvement in photoluminescence intensity relative to the conditions with the stopping range of the implanted ions at the center of the silicon device layer. The previously demonstrated waveguide-integrated LED used implant conditions with the stopping range at the center of this layer. We further show that such light sources can be manufactured at the 300-mm scale by demonstrating photoluminescence of similar intensity from 300 mm silicon-on-insulator wafers. The luminescence uniformity across the entire wafer is within the measurement error.