Showing papers on "Silicon on insulator published in 2021"
TL;DR: In this article, the authors demonstrate ferroelectric memory transistors on a crystalline silicon channel with endurance exceeding 1010 cycles, and demonstrate that appropriate engineering of the interfacial layer could substantially improve FeFET device performance and reliability.
Abstract: We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 1010 cycles. The ferroelectric transistors (FeFETs) incorporate a high- $\kappa $ interfacial layer (IL) of thermally grown silicon nitride (SiNx) and a thin 4.5 nm layer of Zr-doped FE-HfO2 (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of $\text {V}_{\text {G}}= \pm \,\,3\text{V}$ at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.
109 citations
TL;DR: In this paper, the authors demonstrate a spectrally broadband, GHz-fast Mach-Zehnder interferometric modulator, exhibiting a high efficiency signified by a miniscule VπL of 95V μm, deploying a one-micrometer compact electrostatically tunable plasmonic phase shifter, based on heterogeneously integrated ITO thin films into silicon photonics.
Abstract: Densely integrated active photonics is key for next generation on-chip networks for addressing both footprint and energy budget concerns. However, the weak light-matter interaction in traditional active Silicon optoelectronics mandates rather sizable device lengths. The ideal active material choice should avail high index modulation while being easily integrated into Silicon photonics platforms. Indium tin oxide (ITO) offers such functionalities and has shown promising modulation capacity recently. Interestingly, the nanometer-thin unity-strong index modulation of ITO synergistically combines the high group-index in hybrid plasmonic with nanoscale optical modes. Following this design paradigm, here, we demonstrate a spectrally broadband, GHz-fast Mach–Zehnder interferometric modulator, exhibiting a high efficiency signified by a miniscule VπL of 95 V μm, deploying a one-micrometer compact electrostatically tunable plasmonic phase-shifter, based on heterogeneously integrated ITO thin films into silicon photonics. Furthermore we show, that this device paradigm enables spectrally broadband operation across the entire telecommunication near infrared C-band. Such sub-wavelength short efficient and fast modulators monolithically integrated into Silicon platform open up new possibilities for high-density photonic circuitry, which is critical for high interconnect density of photonic neural networks or applications in GHz-fast optical phased-arrays, for example.
34 citations
TL;DR: A 1×64 optical phased array based on a silicon on insulator (SOI) platform with integrated silicon nitride with phase shifter using a silicon waveguide with heater because of the higher thermo-optic coefficient of silicon.
Abstract: We demonstrate a 1×64 optical phased array (OPA) based on a silicon on insulator (SOI) platform with integrated silicon nitride. The input port of the OPA is fabricated using a silicon nitride waveguide due to its advantage of allowing more optical power. The phase shifter is a silicon waveguide with heater because of the higher thermo-optic coefficient of silicon. And a double layer silicon nitride assisted grating is used in the emitter to reduce the emission strength and then increase the length of emitter to reduce the spot size. The length of the grating emitter is 1.5 mm and the measured field of view of this optical phased array is 35.5°×22.7° with spot size of 0.69°×0.075°.
33 citations
TL;DR: In this paper, a low-cost post-fabrication trimming method was proposed to tune the resonance wavelength of a silicon ring resonator and correct for fabrication variations at wafer-scale.
Abstract: Silicon ring resonator-based devices, such as modulators, detectors, filters, and switches, play important roles in integrated photonic circuits for optical communication, high-performance computing, and sensing applications. However, the high sensitivity to fabrication variations has limited their volume manufacturability and commercial adoption. Here, we report a low-cost post-fabrication trimming method to tune the resonance wavelength of a silicon ring resonator and correct for fabrication variations at wafer-scale. We use Ge implant to create an index trimmable section in the ring resonator and an on-chip heater to apply a precise and localized thermal annealing to tune and set its resonance to a desired wavelength. We demonstrate resonance wavelength trimming of ring resonators fabricated across a 300 mm silicon-on-insulator (SOI) wafer to within p32 pm of a target wavelength of 1310 nm, providing a viable path to high-volume manufacturing and opening up new practical applications for these devices.
33 citations
TL;DR: In this article, the authors present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for quantum computing.
Abstract: We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed ${I}_{D}$ dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers.
26 citations
TL;DR: In this paper, a Si PIN diode optical phase shifter under forward biasing at 1550nm wavelength using the standard 220-nm substrate silicon-on-insulator (SOI) rib waveguide technology is presented.
Abstract: Commercial high-speed silicon (Si) Mach-Zehnder modulator (MZM) required to be active around the quadrature bias point (linear transmission area) with low power consumption, small footprint, and small drive voltage. The bias controlling is done by an optical phase-shifter (PS). However, the accuracy is limited by the drive voltage, laser thermal drift, and fabrication errors. To overcome these problems, we propose in this paper the study and analysis of Si PIN diode PS under forward biasing at 1550 nm wavelength using the standard 220 nm substrate silicon-on-insulator (SOI) rib waveguide technology. Numerical investigations were carried out on the key geometrical parameters, doping concentration, doping locations, operating wavelength, biasing level. Results show that the optimal design can be operated with a lower voltage (Vπ = 1.629 v), lower attenuation (α = 28.985 dB/cm), and short device length with an extremely small voltage-length product VπL = 0.815 vmm. Thus, this PS can be used for designing an efficiency high-speed MZM and to obtain better performances in the optical commutation system.
22 citations
TL;DR: In this paper, the current status of GaN HEMT on Si in terms of epitaxy and device performances in high frequency and high power applications is reviewed. And the development and potential benefit of these novel substrates are discussed.
Abstract: GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.
20 citations
TL;DR: In this article, a comprehensive review on recent progress of on-chip PCNC devices for lasing, modulation, switching/filting and label-free sensing is presented, where the authors present a comprehensive overview of the current state-of-the-art.
Abstract: Integrated circuit (IC) industry has fully considered the fact that the Moore’s Law is slowing down or ending. Alternative solutions are highly and urgently desired to break the physical size limits in the More-than-Moore era. Integrated silicon photonics technology exhibits distinguished potential to achieve faster operation speed, less power dissipation, and lower cost in IC industry, because their COMS compatibility, fast response, and high monolithic integration capability. Particularly, compared with other on-chip resonators (e.g. microrings, 2D photonic crystal cavities) silicon-on-insulator (SOI)-based photonic crystal nanobeam cavity (PCNC) has emerged as a promising platform for on-chip integration, due to their attractive properties of ultra-high Q/V, ultra-compact footprints and convenient integration with silicon bus-waveguides. In this paper, we present a comprehensive review on recent progress of on-chip PCNC devices for lasing, modulation, switching/filting and label-free sensing, etc.
20 citations
TL;DR: In this article, a path forward in integrating III-V functionalities on industry-standard silicon-on-insulator (SOI) platforms using selective area hetero-epitaxy was investigated.
Abstract: Epitaxially integrating III-V lasers with Si-photonics is the key for compact, efficient, and scalable photonic integrated circuits (PICs). Here we present an investigation of a path forward in integrating III-V functionalities on industry-standard silicon-on-insulator (SOI) platforms using selective area hetero-epitaxy. Based on our recently developed methods of selectively growing device quality InP on (001)-oriented SOI wafers, we demonstrated InP stripes and segments, with dimensions varying from a few hundred nanometers to a few micrometers. The flexible epitaxy of InP on SOI together with the unique “bufferless” trait will enable efficient light interfacing with Si-based photonic devices using either evanescent or butt coupling schemes. We simulated the possibility of employing the micrometer-scale InP on insulator to realize electrically driven lasers and found that the metal induced optical loss is negligible when the InP dimension exceeds 4.0 μm. The potential of utilizing this selective area growth method to realize fully integrated Si-photonics is illustrated.
19 citations
20 Sep 2021
TL;DR: In this paper, the authors demonstrate III-V photodetectors (PDs) directly grown on a InP/Si-on-insulator (SOI) platform parallel to the Si device layer in a variety of device dimensions.
Abstract: Integrating light emission and detection functionalities using efficient III-V materials on Si wafers is highly desirable for Si-based photonic integrated circuits. To fulfill the need of high-performance photodetectors (PDs) monolithically integrated on Si for Si photonics, we demonstrate III-V PDs directly grown on a InP/Si-on-insulator (SOI) platform parallel to the Si device layer in a variety of device dimensions. Device characteristics including a 3 dB bandwidth beyond 40 GHz, open eye diagrams at 40 Gb/s, a dark current of 0.55 nA, a responsivity of 0.3 A/W at 1550 nm, and 0.8 A/W at 1310 nm together with a 410 nm operation wavelength span from 1240 nm to 1650 nm are achieved. We further simulate the feasibility of interfacing the III-V PDs with the Si waveguide by designing waveguide-coupled PDs with butt coupling schemes. These results point to a practical solution for the monolithic integration of III-V active components and Si-based passive devices on a InP/SOI platform in the future.
19 citations
20 Jun 2021
TL;DR: In this article, the authors demonstrate a high-performance tunable Raman laser on a sub-micrometer-thick silicon on insulator wafer using a standard foundry process.
Abstract: Stimulated Raman scattering is an effective means of wavelength conversion and can largely extend the operating spectral range of an optical source. We demonstrate a high-performance tunable Raman laser on a sub-micrometer-thick silicon on insulator wafer using a standard foundry process. The key feature to this laser is the use of a tunable coupling mechanism to adjust both pump and signal coupling coefficients in the ring cavity, allowing demonstration of laser emission over a large wavelength tuning range of 83 nm. This Raman laser demonstrates efficient (slope of up to 26% and a maximum pump-to-signal power conversion efficiency of 10%) on-chip nonlinear wavelength conversion. Our results indicate great promise for substantially increasing the optical spectral resources available on a silicon chip.
TL;DR: In this article, a piezoresistive pressure sensor based on silicon on insulator (SOI) was presented, which was composed of an SOI layer with sensing elements and a glass cap for a hermetic package.
Abstract: In this paper, a piezoresistive pressure sensor based on silicon on insulator (SOI) was presented, which was composed of an SOI layer with sensing elements and a glass cap for a hermetic package. Different from its conventional counterparts, the position and thickness of the four piezoresistors was optimized based on numerical simulation, which suggests that two piezoresistors at the center while the other two at the edge of the pressure-sensitive diaphragm and a thickness of 2 μm can produce the maximum sensitivity and the minimum nonlinearity. Due to the use of silicon rather than metal for electrical connections, the piezoresistive pressure sensor was fabricated in a highly simplified process. From the experimental results, the fabricated piezoresistive pressure sensor demonstrated a high sensitivity of 37.79 mV·V−1·MPa−1, a high full-scale (FS) output of 472.33 mV, a low hysteresis of 0.09% FS, a good repeatability of 0.03% FS and a good accuracy of 0.06% FS at 20 °C. A temperature coefficient of sensitivity of 0.44 mV·MPa−1·°C−1 and a low zero drift were also shown at different temperatures. The piezoresistive pressure sensor developed in this study may function as an enabling tool in pressure measurements.
TL;DR: In this article, a phase shifter with an effective capacitance (C eff) around 0.5 fF/μm and phase change efficiency 1.8 V ·cm was proposed.
Abstract: This article analysed and optimised horizontal Silicon insulator Silicon capacitor (H-SISCAP) phase shifter structures with insulator thickness tox up to 40 nm. The phase shifter has an effective capacitance ( C eff) around 0.5 fF/μm and a phase change efficiency 1.8 V ·cm, of which the balance between capacitance and phase efficiency is comparable with silicon rib waveguide based depletion type phase shifters. Silicon Mach–Zehnder interferometer (MZI) modulators with 200 μm long H-SISCAP phase shifters optimised for TM polarised light have been fabricated and demonstrated with a 3 dB EO bandwidth above 35 GHz and intrinsic H-SISCAP RC bandwidth around 150 GHz. The modulator displays open eye-diagrams for data rates up to 60 Gbit/s without detection equalization and 72 Gbit/s with 2 taps equalization in NRZ-OOK operation. The demonstrated H-SISCAP phase shifter paves the way to build high bandwidth segmented, travelling wave and compact ring resonators modulators for applications of optical transmitters, microwave generations, and LIDAR applications, etc.
TL;DR: It is theoretically and experimentally proved that Newton's law of cooling can be inadequate in monolithic planar devices, leading to inaccurate predictions.
Abstract: The temporal dynamics of integrated silicon resonators has been modeled using a set of equations coupling the internal energy, the temperature and the free carrier population. Owing to its simplicity, Newton's law of cooling is the traditional choice for describing the thermal evolution of such systems. In this work, we theoretically and experimentally prove that this can be inadequate in monolithic planar devices, leading to inaccurate predictions. A new equation that we train to reproduce the correct temperature behaviour is introduced to fix the discrepancies with the experimental results. We discuss the limitations and the range of validity of our refined model, identifying those cases where Netwon's law provides, nevertheless, accurate solutions. Our modeling describes the phenomena underlying thermal and free carrier instabilities and is a valuable tool for the engineering of photonic systems which rely on resonator dynamical states, such as all optical spiking neural networks or reservoirs for neuromorphic computing.
TL;DR: In this article, a 2-millimeter-long, single-etched subwavelength-engineered optical antenna with a lateral periodic array of radiative elements is presented.
Abstract: Integrated optical antennas are key components for on-chip light detection and ranging technology (LIDAR). In order to achieve a highly collimated far field with reduced beam divergence, antenna lengths on the order of several millimeters are required. In the high-index contrast silicon photonics platform, achieving such long antennas typically demands weakly modulated gratings with lithographic minimum feature sizes below 10 nm. Here, we experimentally demonstrate a new, to the best of our knowledge, strategy to make long antennas in silicon waveguides using a metamaterial subwavelength grating (SWG) waveguide core loaded with a lateral periodic array of radiative elements. The mode field confinement is controlled by the SWG duty cycle, and the delocalized propagating mode overlaps with the periodic perturbations. With this arrangement, weak antenna radiation strength can be achieved while maintaining a minimum feature size as large as 80 nm. Using this strategy, we experimentally demonstrate a 2-millimeter-long, single-etched subwavelength-engineered optical antenna on a conventional 220 nm SOI platform, presenting a measured far-field beam divergence of 0.1° and a wavelength scanning sensitivity of 0.13°/nm.
TL;DR: In this paper, a CMOS-compatible infrared (IR; 1200-1700 nm) detector based on Ge quantum dots (QDs) decorated on a single Si-nanowire channel on a silicon-on-insulator (SOI) platform with a superior detectivity at room temperature is presented.
Abstract: A CMOS-compatible infrared (IR; 1200-1700 nm) detector based on Ge quantum dots (QDs) decorated on a single Si-nanowire channel on a silicon-on-insulator (SOI) platform with a superior detectivity at room temperature is presented. The spectral response of a single nanowire device measured in a back-gated field-effect transistor geometry displays a very high value of peak detectivity ∼9.33 × 1011Jones at ∼1500 nm with a relatively low dark current (∼20 pA), which is attributed to the fully depleted Si nanowire channel on SOI substrates. The noise power spectrum of the devices exhibits a1/fγ,with the exponent,γshowing two different values of 0.9 and 1.8 owing to mobility fluctuations and generation-recombination of carriers, respectively. Ge QD-decorated nanowire devices exhibit a novel polarization anisotropy with a remarkably high photoconductive gain of ∼104. The superior performance of a Ge QDs/Si nanowire phototransistor in IR wavelengths is potentially attractive to integrate electro-optical devices into Si for on-chip optical communications.
TL;DR: In this paper, a wideband bandpass filter for 5G application is proposed, which is implemented in GF 45-nm CMOS SOI and is a 4-pole/4-zero design which greatly enhance the filter selectivity and out-of-band rejection.
Abstract: In this letter, a wideband bandpass filter for 5G application is proposed. The filter is implemented in GF 45-nm CMOS SOI (silicon-on-insulator) and is a 4-pole/ 4-zero design which greatly enhance the filter selectivity and out-of-band rejection. Measurements show a filter 3-dB bandwidth of 22-44 GHz, and covers the millimeter-wave 5G 26/28/39 GHz bands. The minimum insertion loss is 1.5 dB with a return loss better than 10 dB and a filter size of 0.07 mm2. The work shows that wideband high-performance filter can be integrated as part of the wideband/multiband RF front-end on CMOS SOI.
TL;DR: In this article, a chirped spiral Bragg grating waveguide (SBGW) is proposed and experimentally demonstrated with a measured transmission loss of 0.7 dB/cm.
Abstract: Limited by large transmission loss, the development of transverse electric (TE) mode silicon-on-insulator (SOI) based on-chip long length chirped grating waveguide faces many difficulties now. To overcome this problem, multi-mode waveguide with a measured transmission loss of 0.7 dB/cm is applied in this paper, and a chirped spiral Bragg grating waveguide (SBGW) is proposed and experimentally demonstrated. The length of the chirped SBGW reaches 2.7 cm, which is the longest SOI based grating reported so far. The total group delay is measured to be 628 ps, with a structure size of only 0.3 mm2 due to the application of spiral configuration. The slope of the linear dispersion is -27.7 ps/nm. This integrated chirped SBGW shows great compatibility with frequently used TE mode SOI devices and has great potential for applications in microwave photonics requiring dispersion control.
TL;DR: An n+ pocket-doped silicon on insulator (SOI) tunnel field effect transistor (TFET) along with a dielectric pocket (DP) at channel drain junction has been proposed and investigated in this paper.
Abstract: An n+ pocket-doped silicon on insulator (SOI) tunnel field effect transistor (TFET) along with a dielectric pocket (DP) at channel drain junction has been proposed and investigated in this article. The merged impact of both lateral and vertical tunneling due to n+ pocket in the gate–source overlap region enhances the ON current and provides steeper subthreshold swing (SS). The dielectric pocket at channel drain junction depletes the drain region at channel drain interface. Consequently, the minimum tunneling width at channel drain interface is enhanced to offer significant suppression of ambipolar conduction in a TFET. The proposed TFET structure offers a high ON/OFF current ratio of 1.57 × 1010 and considerably low SS of 8 mV/dec along with reduced ambipolar conduction up to a larger negative bias region. The impact of parametric variation of the proposed structure is studied and optimized accordingly. Noise characteristics of the proposed SOI TFET are investigated to realize the reliability issues of the device. Besides, the impact of elevated temperature on transfer characteristic and various RF parameters including transconductance (gm), total gate capacitance (Cgg), gate to drain capacitance (Cgd), cutoff frequency (ft), gain bandwidth product (GBP) and intrinsic delay (τ), respectively, have been investigated. The device performance has been upgraded by the rise in cutoff frequency and drop in intrinsic delay at high temperature.
TL;DR: In this paper, total ionizing-dose (TID) effects for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors were investigated.
Abstract: Total-ionizing-dose (TID) effects are investigated for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors. Electron trapping in the gate dielectric establishes the programmed memory state for both silicon on insulator (SOI) and bulk devices. To first order, ionizing radiation does not interact strongly with programing-induced charges in the gate dielectric for either device type. Hole trapping in the buried oxide dominates the TID response of the 22-nm FDSOI devices. The 14-nm bulk devices with two fins and total effective fin widths of 150 nm are minimally affected by TID, but the subthreshold leakage of devices with 40 fins and total effective fin widths of $3~\mu \text{m}$ increases with increasing TID. When devices are programmed or reprogrammed after irradiation, significant increases in subthreshold slope are observed due to the generation of interface traps, border traps, and/or charge lateral nonuniformities.
TL;DR: This work proposes a novel geometry to design complex Bragg filters with an arbitrary spectral response in silicon waveguides with laterally coupled Bragg loading segments, and presents an efficient design strategy that allows to readily synthesize an arbitrary target spectrum for the authors' cladding-modulated Bragg gratings.
Abstract: Spectral filters are important building blocks for many applications in integrated photonics, including datacom and telecom, optical signal processing and astrophotonics. Sidewall-corrugated waveguide grating is typically the preferred option to implement spectral filters in integrated photonic devices. However, in the high-index contrast silicon-on-insulator (SOI) platform, designs with corrugation sizes of only a few tens of nanometers are often required, which hinders their fabrication. In this work, we propose a novel geometry to design complex Bragg filters with an arbitrary spectral response in silicon waveguides with laterally coupled Bragg loading segments. The waveguide core is designed to operate with a delocalized mode field, which helps reduce sensitivity to fabrication errors and increase accuracy on synthesized coupling coefficients and the corresponding spectral shape control. We present an efficient design strategy, based on the layer-peeling and layer-adding algorithms, that allows to readily synthesize an arbitrary target spectrum for our cladding-modulated Bragg gratings. The proposed filter concept and design methodology are validated by designing and experimentally demonstrating a complex spectral filter in an SOI platform, with 20 non-uniformly spaced spectral notches with a 3-dB linewidth as small as 210 pm.
TL;DR: In this paper, the impact of source pocket on switching behavior of n-type Ge-source SOI-TFET and shows improvements in the device performance in terms of SS, ION, IOFF and ION/IOFF.
Abstract: As devices are scaled down in nano regime the steepest subthreshold swing becomes the most desirable characteristic for the improvement of the performance of devices. To address this issue, tunnel field effect transistor is one of the promising candidates for replacing conventional MOS device. This paper investigates the impact of source pocket on switching behaviour of n-type Ge-source SOI-TFET and shows improvements in the device performance in terms of SS, ION, IOFF and ION/IOFF. The proposed device is compared with the homojunction SOI-TFET. The improved electrical characteristics of device are analysed on the basis of simulation results and justified by the theoretical concept. The device offers the steepest SS of 11 mV/decade, higher ION of 120 μA, and higher ION/IOFF ratio of 8.64 × 1011. The device characteristics are investigated by using TCAD tool.
10 Sep 2021
TL;DR: In this paper, a review of the recent developments in field effect transistors (FETs) for gas and volatile organic compound (VOC) sensing is presented, where the Si channel is either a part of the silicon on insulator (SOI) or the bulk Si.
Abstract: Highly sensitive and selective gas and volatile organic compound (VOC) sensor platforms with fast response and recovery kinetics are in high demand for environmental health monitoring, industry, and medical diagnostics. Among the various categories of gas sensors studied to date, field effect transistors (FETs) have proved to be an extremely efficient platform due to their miniaturized form factor, high sensitivity, and ultra-low power consumption. Despite the advent of various kinds of new materials, silicon (Si) still enjoys the advantages of excellent and reproducible electronic properties and compatibility with complementary metal–oxide–semiconductor (CMOS) technologies for integrated multiplexing and signal processing. This review gives an overview of the recent developments in Si FETs for gas and VOC sensing. We categorised the Si FETs into Si nanowire (NW) FETs; planar Si FETs, in which the Si channel is either a part of the silicon on insulator (SOI) or the bulk Si, as in conventional FETs; and electrostatically formed nanowire (EFN) FETs. The review begins with a brief introduction, followed by a description of the Si NW FET gas and VOC sensors. A brief description of the various fabrication strategies of Si NWs and the several functionalisation methods to improve the sensing performances of Si NWs are also provided. Although Si NW FETs have excellent sensing properties, they are far from practical realisation due to the extensive fabrication procedures involved, along with other issues that are critically assessed briefly. Then, we describe planar Si FET sensors, which are much closer to real-world implementation. Their simpler device architecture combined with excellent sensing properties enable them as an efficient platform for gas sensing. The third category, the EFN FET sensors, proved to be another potential platform for gas sensing due to their intriguing properties, which are elaborated in detail. Finally, the challenges and future opportunities for gas sensing are addressed.
TL;DR: A systematic analysis of phosphorus diffusion in silicon on insulator thin film via spin-on-dopant process (SOD) finds that a high phosphorous concentration with a limited diffusion of other chemical species and allowing to tune the electrical properties via annealing at high temperature for short time.
Abstract: We report on a systematic analysis of phosphorus diffusion in silicon on insulator thin film via spin-on-dopant process (SOD). This method is used to provide an impurity source for semiconductor junction fabrication. The dopant is first spread into the substrate via SOD and then diffused by a rapid thermal annealing process. The dopant concentration and electron mobility were characterized at room and low temperature by four-probe and Hall bar electrical measurements. Time-of-flight-secondary ion mass spectroscopy was performed to estimate the diffusion profile of phosphorus for different annealing treatments. We find that a high phosphorous concentration (greater than 1020 atoms cm-3) with a limited diffusion of other chemical species and allowing to tune the electrical properties via annealing at high temperature for short time. The ease of implementation of the process, the low cost of the technique, the possibility to dope selectively and the uniform doping manufactured with statistical process control show that the methodology applied is very promising as an alternative to the conventional doping methods for the implementation of optoelectronic devices.
TL;DR: In this paper, the spin lifetime anisotropy of propagating spins in the Si MOS was observed to form an emergent effective magnetic field due to the spin-orbit interaction.
Abstract: The spin–orbit interaction (SOI), mainly manifesting itself in heavy elements and compound materials, has been attracting much attention as a means of manipulating and/or converting a spin degree of freedom. Here, we show that a Si metal-oxide- semiconductor (MOS) heterostructure possesses Rashba-type SOI, although Si is a light element and has lattice inversion symmetry resulting in inherently negligible SOI in bulk form. When a strong gate electric field is applied to the Si MOS, we observe spin lifetime anisotropy of propagating spins in the Si through the formation of an emergent effective magnetic field due to the SOI. Furthermore, the Rashba parameter α in the system increases linearly up to 9.8 × 10−16 eV m for a gate electric field of 0.5 V nm−1; that is, it is gate tuneable and the spin splitting of 0.6 μeV is relatively large. Our finding establishes a family of spin–orbit systems. Silicon is a light element with high lattice inversion symmetry, and so is not expected to possess a substantial spin–orbit interaction (SOI), which is desirable for spintronics. Here, a silicon-based heterostructure is demonstrated to have a gate-tuneable Rashba-type SOI.
TL;DR: In this paper, a dual-band grating coupler fabricated using 193 nm deep-ultraviolet lithography for 10 Gbit symmetric passive optical networks is presented. But the efficiency of the coupler is limited by the wavelength-dependent radiation angle.
Abstract: Surface grating couplers are fundamental building blocks for coupling the light between optical fibers and integrated photonic devices. However, the operational bandwidth of conventional grating couplers is intrinsically limited by their wavelength-dependent radiation angle. The few dual-band grating couplers that have been experimentally demonstrated exhibit low coupling efficiencies and rely on complex fabrication processes. Here we demonstrate for the first time, to the best of our knowledge, the realization of an efficient dual-band grating coupler fabricated using 193 nm deep-ultraviolet lithography for 10 Gbit symmetric passive optical networks. The footprint of the device is 17×10µm2. We measured coupling efficiencies of −4.9 and −5.2dB with a 3-dB bandwidth of 27 and 56 nm at the wavelengths of 1270 and 1577 nm, corresponding to the upstream and downstream channels, respectively.
05 Mar 2021
TL;DR: In this article, a large-area transfer-free, layer-by-layer method was used to integrate two-dimensional (2D) graphene oxide (GO) films with silicon-on-insulator nanowires (SOI), high index doped silica glass (Hydex) and silicon nitride (SiN) waveguides and ring resonators.
Abstract: We report enhanced nonlinear optics in complementary metal-oxide-semiconductor (CMOS) compatible photonic platforms through the use of layered two-dimensional (2D) graphene oxide (GO) films. We integrate GO films with silicon-on-insulator nanowires (SOI), high index doped silica glass (Hydex) and silicon nitride (SiN) waveguides and ring resonators, to demonstrate an enhanced optical nonlinearity including Kerr nonlinearity and four-wave mixing (FWM). The GO films are integrated using a large-area, transfer-free, layer-by-layer method while the film placement and size are controlled by photolithography. In SOI nanowires we observe a dramatic enhancement in both the Kerr nonlinearity and nonlinear figure of merit (FOM) due to the highly nonlinear GO films. Self-phase modulation (SPM) measurements show significant spectral broadening enhancement for SOI nanowires coated with patterned films of GO. The dependence of GO’s Kerr nonlinearity on layer number and pulse energy shows trends of the layered GO films from 2D to quasi bulk-like behavior. The nonlinear parameter of GO coated SOI nanowires is increased 16 folds, with the nonlinear FOM increasing over 20 times to FOM > 5. We also observe an improved FWM efficiency in SiN waveguides integrated with 2D layered GO films. FWM measurements for samples with different numbers of GO layers and at different pump powers are performed, achieving up to ≈7.3 dB conversion efficiency (CE) enhancement for a uniformly coated device with 1 layer of GO and ≈9.1 dB for a patterned device with 5 layers of GO. These results reveal the strong potential of GO films to improve the nonlinear optics of silicon, Hydex and SiN photonic devices.
TL;DR: In this article, a gate-all-around metal-oxide-semiconductor field effect transistor (GAA MOSFET) based on void embedded silicon on insulator (VESOI) substrate is demonstrated.
Abstract: A novel method for manufacturing gate-all-around metal-oxide-semiconductor field effect transistor (GAA MOSFET) based on void embedded silicon on insulator (VESOI) substrate is demonstrated in this work. VESOI with embedded submicron void chambers has been designed to fabricate suspended silicon channels by a one-step lithography and dry etching process. GAA MOSFET built on VESOI substrate exhibits excellent characteristics with subthreshold swing (SS) about 63mV/dec, ON/OFF ratio of 1010, drain-induced barrier lowering (DIBL) less than 12mV/V and strong tolerance to back gate bias. This method shows significant advantages to fabricate suspended Si channels, and can be readily extended to other types of material systems for low-power and high-performance applications.
09 May 2021
TL;DR: In this paper, the authors experimentally measured the radiation of optical phased arrays fabricated on a SOI waveguide platform and realized one-dimensional beam steering and observed standing-wave patterns in the waveguide antennas.
Abstract: We experimentally measured the radiation of optical phased arrays fabricated on SOI waveguide platform. By tuning the input laser wavelength, we realized one-dimension beam steering and observed standing-wave patterns in the waveguide antennas.