Topic
Silicon on insulator
About: Silicon on insulator is a research topic. Over the lifetime, 19592 publications have been published within this topic receiving 302534 citations. The topic is also known as: SOI.
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TL;DR: In this article, a silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen.
Abstract: A silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen. The basic phenomena, and the first physical and electrical characterisations are discussed briefly.
1,106 citations
IBM1
TL;DR: The fabrication and accurate measurement of propagation and bending losses in single-mode silicon waveguides with submicron dimensions fabricated on silicon-on-insulator wafers with record low numbers can be used as a benchmark for further development of silicon microphotonic components and circuits.
Abstract: We report the fabrication and accurate measurement of propagation and bending losses in single-mode silicon waveguides with submicron dimensions fabricated on silicon-on-insulator wafers. Owing to the small sidewall surface roughness achieved by processing on a standard 200mm CMOS fabrication line, minimal propagation losses of 3.6+/-0.1dB/cm for the TE polarization were measured at the telecommunications wavelength of 1.5microm. Losses per 90 masculine bend are measured to be 0.086+/-0.005dB for a bending radius of 1microm and as low as 0.013+/-0.005dB for a bend radius of 2microm. These record low numbers can be used as a benchmark for further development of silicon microphotonic components and circuits.
999 citations
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >
921 citations
TL;DR: In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.
Abstract: In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.
878 citations
IBM1
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.
861 citations