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Silicon on insulator

About: Silicon on insulator is a research topic. Over the lifetime, 19592 publications have been published within this topic receiving 302534 citations. The topic is also known as: SOI.


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Patent
William F. Clark1, Edward J. Nowak1
28 Apr 2005
TL;DR: In this article, a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology is described, which includes a substrate having a buried insulator layer formed over the substrate and an active layer formed on top of the active layer.
Abstract: Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.

4 citations

Journal ArticleDOI
TL;DR: In this paper, a novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τg) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor.
Abstract: A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τg) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τg measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron–hole droplet in the band-edge emission.

4 citations

Proceedings ArticleDOI
04 Oct 1999
TL;DR: In this article, the intrinsic and extrinsic threshold voltage (V/sub ts/) fluctuations in fully depleted (FD) single gate (SG) and dual gate (DG) SOI MOSFETs as well as partially depleted (PD) MOSFLETs are investigated using novel 3D compact physical models.
Abstract: Intrinsic and extrinsic threshold voltage (V/sub ts/) fluctuations in fully depleted (FD) single gate (SG) and dual gate (DG) SOI MOSFETs as well as partially depleted (PD) SOI MOSFETs are investigated using novel 3D compact physical models. Threshold voltage maximum deviations due to intrinsic random dopant placement can escalate to more than /spl plusmn/100% for sub-100 nm technology generations. Much smaller (<1.5 mV) intrinsic threshold voltage fluctuations in undoped SOI MOSFETs are explored.

4 citations

Proceedings ArticleDOI
01 Jan 2006
TL;DR: In this article, the steady state temperature profiles of U-and I-shaped electrothermal microactuators are analyzed for various input voltage amplitudes. And the performance sensitivity of the micro-actuator due to various parameter changes is evaluated.
Abstract: The steady state temperature profiles of U- and I-shaped electrothermal microactuators are analytically derived. The temperature profiles could be used to evaluate the performance sensitivity of the microactuator due to various parameter changes. In this work, the analysis assumes an unpackaged silicon microactuator with an air gap between the actuator and substrate and the profiles are evaluated for various input voltage amplitudes. It was found that at low voltage inputs the temperature profile is exponential in nature with the failure being due to thermo-structural stresses and/or structure melting. At voltages larger than a critical value, a combined sinusoidal and exponential temperature profile is observed with the failure being strongly due to structural melting as well. However, higher voltage excitation causes a fully distributed sinusoidal temperature profile. In this mode, failures occur at different locations and due to high localized thermal stresses causing the temperature to exceed the material melting point. The behavior of U- and I-shaped microactuators based on silicon on insulator (SOI) fabrication and femtosecond laser micromachining was experimentally examined with the results corroborating the conclusions drawn from the analysis.© 2006 ASME

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023325
2022767
2021282
2020372
2019462
2018492