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Showing papers on "Silicon oxide published in 1969"


Journal ArticleDOI
TL;DR: Recording ellipsometers and surface film balance, breath patterns, and ferric oxide powder “staining” were used to observe adsorption of normal plasma constituents onto metal oxide, silicon oxide, and polymer surfaces.
Abstract: Recording ellipsometers and surface film balance, breath patterns, and ferric oxide powder “staining” were used to observe adsorption of normal plasma constituents onto metal oxide, silicon oxide, and polymer surfaces. Adsorbed proteins could be identified by their ability to adsorb matter from corresponding antihuman sera. Data indicate that oxidized silicon crystal surfaces adsorbed fibrinogen out of plasmas within 2 sec; within 20 sec, these films lost their ability to attract antifibrinogen and were later partially removed if intact factor XII was present in the solution. One aminated nonheparinized polymer formed films that adsorbed large amounts of fibrinogen and some gamma globulins out of plasma in the ellipsometer, and platelets out of platelet-rich plasma, as well as ferric oxide out of aqueous suspension. After taking up heparin, these polymer films appeared able to adsorb only small amounts of protein or oxide, and no detectable amounts of fibrinogen or platelets. On another aminated polymer, heparin seemed without effect. Interaction of metal surfaces with plasma may be complicated by oxidation.

406 citations


Journal ArticleDOI
TL;DR: In this article, a mechanism of hopping conduction is proposed to explain these results and to link with the d.c. results reported earlier on the same material, which are attributed to electronic hopping and one is associated with space charge injection.

122 citations


Patent
22 Jul 1969
TL;DR: In this article, a polycrystalline semiconductor surface layer is employed as a mask for the diffusion of the source and drain regions, thereby insuring automatic alignment between the gate electrode and the source or drain regions.
Abstract: Insulated Gate Field Effect Transistor employing a polycrystalline semiconductor surface layer, one strip of which serves as the gate electrode of the IGFET, and another strip of which may serve as a resistor. The semiconductor surface layer is employed as a mask for the diffusion of the source and drain regions, thereby insuring automatic alignment between the gate electrode and the source and drain regions.

64 citations


Patent
13 Mar 1969
TL;DR: In this article, a process for forming a film on the surface of a substrate by a gas phase method in the presence of a catalyst used in the solid state electronics at a predetermined distance from the substrate on which the film is to be formed is described.
Abstract: A process for forming a film on the surface of a substrate by a gas phase method in the presence of a catalyst used in the solid state electronics at a predetermined distance from the surface of the substrate on which the film is to be formed and a process for forming a silicon oxide or silicon nitride in the presence of a catalyst selected from the group comprising platinum and the like.

54 citations


Journal ArticleDOI
TL;DR: In this paper, a simple two-layer model is presented for charge storage in a MI2I1S device in which the times for charging and discharging are expressed in closed-form expressions depending on the conduction properties, the thicknesses, and the dielectric constants of the two layers.
Abstract: A simple two‐layer model is presented for charge storage in a MI2I1S device in which the times for charging and discharging are expressed in closed‐form expressions depending on the conduction properties, the thicknesses, and the dielectric constants of the two layers. Data were taken using silicon oxide for I1 and silicon nitride for I2 which are in good agreement with the model. The model is quite general and should be valid for other insulators and other conduction mechanisms.

52 citations


Patent
20 Oct 1969
TL;DR: In this article, a coherent solid layer of an oxide of silicon was deposited upon a surface of a substrate by establishing a glow discharge adjacent to said surface in an atmosphere containing a gaseous compound of the element or elements comprising the material.
Abstract: This is a method of depositing a coherent solid layer of an oxide of silicon deposited upon a surface of a substrate by establishing a glow discharge adjacent to said surface in an atmosphere containing a gaseous compound of the element or elements comprising the material.

38 citations


Journal ArticleDOI
TL;DR: In this paper, it was shown that at the surface of thin silicon oxide films grown on silicon, oxide ions provide a layer of negative charge; an equal positive charge (usually sodium ions) is concentrated in the oxide within about 200 A of the surface.

33 citations



Journal ArticleDOI
TL;DR: In this paper, an experimental method for determining the depletion depth in thin films of cadmium selenide is used to measure simultaneous variation of conductivity and the space-charge region.
Abstract: An experimental method for determining the depletion depth in thin films of cadmium selenide is used to measure simultaneous variation of conductivity and the space-charge region. The temperature dependence of the conductance reveals donor levels distributed about 0.10 eV and 0.50 eV. Total depletion of films a few thousand angstroms thick produced by oxygen adsorption occurs by exhaustion of the shallow donors. Following exposure to the atmosphere at room temperature, the film conductance decreases by two orders of magnitude when heated in vacuum above 70°C. The subsequent time dependence of the current is shown to follow an Elovich-type relation. This effect is interpreted as conversion of physically adsorbed oxygen to chemisorbed oxygen. The role of evaporated silicon oxide layers in the prevention of the conversion process is discussed. The instability in thin film transistor threshold voltage above 200°C is described in terms of an interface desorption model.

26 citations


Journal ArticleDOI
Masahiro Okamura1
TL;DR: The diffusion coefficient of boron in silicon oxide is smaller than that in silicon by three orders of magnitude, and the activation energy of the diffusion is about 36 kcal, which is less than half of that reported previously.
Abstract: Boron diffusion into silicon has been investigated by a closed tube method using elemental boron as the source. Amount of the source, source temperature, and diffusion temperature are the main parameters controlling the surface concentration. It is presumably boron oxide formed by oxidation of the source boron that actually contributes to boron transfer in a closed tube system. The diffusion coefficient of boron in silicon is given by D=5.1exp (-85,000/RT), and its concentration dependence is examined. The masking effect of silicon oxide against boron diffusion is also examined on the basis of the two boundary diffusion model. The diffusion coefficient of boron in silicon oxide is smaller than that in silicon by three orders of magnitude, and the activation energy of the diffusion is about 36 kcal, which is less than a half of that reported previously.

25 citations


Patent
05 May 1969
TL;DR: A silicon solar cell array, having the substrate, the cellsupporting grid structure, the electrical connecting leads, cell contacts, and the terminal connections all fabricated from low atomic material such as aluminum, beryllium, or magnesium, having glass, silicon oxide and anodized aluminum insulation; silicone adhesives; and having ultrasonic welded electrical connections, is relatively impervious to damage from space nuclear blast radiation as discussed by the authors.
Abstract: A silicon solar cell array, having the substrate, the cellsupporting grid structure, the electrical connecting leads, the cell contacts, and the terminal connections all fabricated from low atomic material such as aluminum, beryllium, or magnesium, having glass, silicon oxide and anodized aluminum insulation; silicone adhesives; and having ultrasonic welded electrical connections provides a hardened silicon solar cell array that is relatively impervious to damage from space nuclear blast radiation.

Patent
27 Aug 1969
TL;DR: In this paper, a stabilized semiconductor device and method of fabrication is disclosed in which a suitably doped silicon oxide stabilization layer for effecting surface passivation is disposed over a surface of a semiconductor devices and separated from the surface by a relatively thin layer of silicon oxide to prevent deleterious levels of impurities from diffusing into the surface from the doped stabilization layer.
Abstract: A stabilized semiconductor device and method of fabrication is disclosed in which a suitably doped silicon oxide stabilization layer for effecting surface passivation is disposed over a surface of a semiconductor device and separated from the surface by a relatively thin layer of silicon oxide to prevent deleterious levels of impurities from diffusing into the surface from the doped stabilization layer.

Patent
Norman I Gri, Eugene T Yon1
03 Jul 1969
TL;DR: In this article, an indium antimonide infrared detector with a novel contact region is presented, where a silicon oxide layer is disposed over most of the anodized surface oxide film but exposes a portion of the P-region which portion comprises superimposed layers of chromium and gold which form the contact region.
Abstract: The invention here disclosed is an indium antimonide infrared detector having a novel contact region. The detector comprises a substrate, constituted of an N-material with a P-region fused thereon. An anodized surface oxide film is superimposed over the diffused P-region and over the adjacent surface of the substrate. A silicon oxide layer is disposed over most of the anodized surface oxide film but exposes a portion of the P-region which portion comprises superimposed layers of chromium and gold which form the contact region, said layers masking the contact area and rendering it insensitive to infrared radiation and simultaneously providing a pad to which an electrical connection may conveniently be made.

Journal ArticleDOI
TL;DR: In this article, the development of "cermet" film resistors prepared by deposition in vacuum is discussed, and the properties of the samples are discussed, in particular both their long and short-term stability, their conduction mechanisms, and methods of adjusting the temperature coefficient of resistance.

Journal ArticleDOI
TL;DR: In this article, DC and AC conduction measurements were made on films of silicon oxide which had been fully annealed and four activation energies were determined for the conduction processes.
Abstract: DC and AC conduction measurements were made on films of silicon oxide which had been fully annealed. Four activation energies were determined for the conduction processes. In the case of DC conduction a time-dependent absorption current was observed at low fields and this was related to a low-frequency dispersion. The steady-state current at low fields was ohmic. At high fields the conductivity was field-dependent and the usual Jα exp (βV1/2) relationship was observed.

Patent
12 Mar 1969
TL;DR: In this paper, a gap spacer between magnetic core members is defined, which spacer is constituted by at least one layer of a nonmagnetic metal oxide formed over a protective layer, such as, silica dioxide, on a gap-defining surface.
Abstract: A magnetic head has a gap spacer between magnetic core members thereof, which spacer is constituted by at least one layer of a nonmagnetic metal oxide formed over a protective layer, such as, silica dioxide, on a gap-defining surface of the magnetic core members. The metal oxide layer is formed over the protective layer by heating on the latter an acid solution of a nonmagnetic metal halide or a solution of an organic metal salt, during which heating the protective layer prevents oxidation and etching of the underlying gap-defining surface.

Journal ArticleDOI
01 Sep 1969
TL;DR: In this article, the effect of ion migration on the oxide layer and the Si-SiO 2 interface in a MOS configuration was investigated using a photoelectric technique. But the results of the study were limited to a single layer.
Abstract: The growth of oxide layers on silicon is frequently carried out during the fabrication of integrated circuits. This paper describes the results of the study of the oxide layer and the Si-SiO 2 interface in a MOS configuration, by a photoelectric technique. The interface barrier height and the built-in voltage V MS in the oxide layer of a MOS structure are measured. The effect of ion migration has been studied by subjecting the structure to bias-heat (BH) treatment. We have constructed the band energy diagram for a p-type 0.001 Ω ċ cm MOS structure, both before and after BH treatment. The photoelectric technique is found to be a convenient tool to study and compare different oxidation processes.

Patent
27 May 1969
TL;DR: In this paper, a palladium film of a predetermined shape can be formed on a semiconductor body by forming a silicon oxide film on the body, making a contact window of desired shape in the oxide film to expose the semiconductor bodies, then depositing palladium on the surface of the body and the oxide layer and then subjecting the assembly to a gas containing hydrogen thereby to peel off that part of the Palladium film which is on the silicon oxide layer.
Abstract: A palladium film deposited on a silicon oxide layer peels off when subjected to a gas containing hydrogen. A palladium film of a predetermined shape can be formed on a semiconductor body by forming a silicon oxide film on the body, making a contact window of desired shape in the oxide film to expose the semiconductor body, then depositing palladium on the body and the oxide film and then subjecting the assembly to a gas containing hydrogen thereby to peel off that part of the palladium film which is on the silicon oxide film leaving the palladium film which is on the contact window.

Patent
06 Mar 1969
TL;DR: A BISMUTH MOLYBDATE- or bISMUTH PHOSPHOMOLY-BDATEon-TITANIA CATALYST is made by MIXING a TITANIA sol with COMPOUNDS to give an AQUEOUS SLURRY as discussed by the authors.
Abstract: A BISMUTH MOLYBDATE- OR BISMUTH PHOSPHOMOLYBDATEON-TITANIA CATALYST IS MADE BY MIXING A TITANIA SOL WITH COMPOUNDS TO GIVE AN AQUEOUS SLURRY WHICH PRODUCES, AFTER DRYING AND CALCINING, BISMUTH OXIDE, MOLYBDENUM OXIDE AND OPTIONALLY SILICON OXIDE AND PHOSPHORUS OXIDE, IN THE DESIRED PROPORTIONS. A PREFERRED METHOD OF PREPARING THE CATALYST IS TO ADD, PRIOR TO DRYING, AMMONIUM CARBONATE, OR AQUEOUS AMMONIA, TO THE SLURRY UNTIL THE PH IS IN THE RANGE OF 5-7.5. SUBSEQUENTLY THE CATALYST IS DRIED AND CALCINED AT TEMPERATURES ABOVE 600* BUT BELOW 700*C. THE RESULTING CATALYST HAS THE FORMULA: BIAPBMO12(TI1-XSIX)COD WHERE A IS EQUAL TO OR GREATER THAN 4, B IS 0 TO 2, C IS 6 TO 80, D IS 1.5A+2.5B+36+2C AND X IS 0 TO 0.5. THE CATALYST PRODUCED IS USEFUL IN VARIOUS OXIDATION REACTIONS, E.G. METHANOL TO FORMALDEHYDE.

Patent
03 Jan 1969
TL;DR: In this article, the authors present a semi-conductor with an apertured coating of a silicon oxide, nitride, or oxide-nitride, which is applied to the entire surface at a substrate temperature of 100-500‹C.
Abstract: 1,269,130. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 17 Nov., 1969 [3 Jan., 1969], No. 56104/69. Heading H1K. Ohmic contact to a semi-conductor body is made within an aperture in a surface insulating layer by a layer of silicon monoxide-chromium cermet overcoated with a metal layer. A silicon or germanium body may be provided with an apertured coating of a silicon oxide, nitride, or oxide-nitride, or of a silicate glass. The cermet is applied to the entire surface at a substrate temperature of 100-500‹C. by flash evaporation of a sintered mixture of its two components or by coevaporation of the two components from separate sources. The chromium content of the cermet may be 50-90 atomic per cent. Without breaking vacuum, a layer of copper, silver or gold is applied and may be followed by a flashed layer of chromium or titanium. After selective etching to leave a contact and track pattern (resistors are formed in the pattern by the removal of the metallic layers to leave the cermet only), the system is baked for 1 hour at 300- 500‹ C. to effect diffusion of cermet components into the semi-conductor. A single- or multiplelayer insulation is applied and apertures formed at terminal areas. Further interconnection levels may be provided.

Patent
15 Jul 1969
TL;DR: In this paper, a surface coating consisting of a silicon nitride film and a silicon oxide film covering different surface portions of a semiconductor substrate of silicon is used for selective diffusion of impurities such as gallium and antimony.
Abstract: A semiconductor element having a surface coating consisting of, for example, a silicon nitride film and a silicon oxide film covering different surface portions of a semiconductor substrate of, for example, silicon so that such surface coating can be utilized for selective diffusion of impurities such as gallium and antimony. In a semiconductor device thus formed, the surface coating acts as a satisfactory surface protective film against external atmosphere, and the backward characteristics of the PN junction can be improved because the end edge of the PN junction terminating at the substrate surface is covered with the silicon nitride film.

Patent
29 Aug 1969
TL;DR: In this paper, the authors show that a SILCONSTRATE and PHOSPHORUS OXIDE can react to any MOISTURE in the external ATMOSPHERE.
Abstract: THIS SPECIFICATION DISCLOSES A SEMICONDUCTOR DEVICE COMPRISING A SILCON SUBSTRATE, AN INSULATING FILM CONTAINING SILCON OXIDE AND PHOSPHOURS OXIDE WHICH IS FORMED ON THE SURFACE OF SAID SILCON SUBSTRTE, AND A PROTECTIVE COATING CONTAINING ALUMINUM OXIDE WHICH IS FORMED ON THE INSULATING FILM. IN THE SEMICONDUCTOR DEVICE OF THIS INVENTION, SAID PROTECTIVE COATING CONTAINING ALUMINUM OXIDE SERVES TO PREVENT SAID INSULATING FILM CONTAINING SILICON OXIDE AND PHOSPHORUS OXIDE FROM REACTING WITH ANY MOISTURE IN THE EXTERNAL ATMOSPHERE, THEREBY IMPROVING THE WATER RESISTING PROPERTY OF THE SEMICONDUCTOR DEVICE AND STABILISING THE SEMICONDUCTOR SURFACE CHARACTERISTICS OF THE LATTER.

Patent
30 Apr 1969
TL;DR: In this paper, a method for manufacturing a semiconductor device whose surface is passivated by a silicon oxide film, forming a pyrolytic silicon oxide films on the surface of the semiconductor substrate at a temperature no higher than 900* C, was proposed.
Abstract: A method for manufacturing a semiconductor device whose surface is passivated by a silicon oxide film, forming a pyrolytic silicon oxide film on the surface of a semiconductor substrate at a temperature no higher than 900* C., depositing phosphorus oxide from a vapor phase containing phosphorus at a temperature no higher than 900* C. on the surface of said silicon oxide film, and causing a reaction between the surface layer of silicon oxide and phosphorus oxide at a temperature no higher than 900* c., thereby forming in the surface of said deposited film a glass layer mixed with phosphorus oxide and silicon oxide.

Patent
09 Jun 1969
TL;DR: A semi-conductor body containing silicon as a component is contacted by fusing it to a contact member of molybdenum disilicide, tungsten disilicides, or a higher silicon content variant of, these materials, which is covered, except for the contact region, with a coating of silicon oxide.
Abstract: 1,106,287. Semi-conductor devices. SIEMENS-SCHUCKERTWERKE A.G. 13 June, 1966 [11 June, 1965], No. 26335/66. Heading H1K. A semi-conductor body containing silicon as a component is contacted by fusing it to a contact member of molybdenum disilicide, tungsten disilicide, or a higher silicon content variant of, these materials, which is covered, except for the contact region, with a coating of silicon oxide. As shown, a thermoelectric device comprises two limbs 4, 5 of germanium-silicon fused to contact members 6, 7 and 8 of molybdenum disilicide each of which is coated with a layer 9, 10, 11 of silicon oxide. The contact members are prepared by rapidly heating a preshaped body of molybdenum silicide to about 1500‹ C. in an oxidizing atmosphere. Molybdenum oxide evaporates from the surface leaving a skeleton layer of silicon which is oxidized to form an insulating glaze. After cooling, the glaze is mechanically removed from the contact areas to which the semi-conductor bodies are fused. Foil or gauze inserts 12, 13, 14, 15 of molybdenum (or tungsten if the contact members are of tungsten disilicide) may be placed between the semi-conductor bodies and the contact members before forming the fused contacts. One of the germanium-silicon bodies 4, 5 may be doped with boron, gallium or indium, and the other may be doped with phosphorus, arsenic or antimony. Heat exchangers 2, 3 are applied directly to the insulated surfaces of the contact members.

Patent
Takashi Tsuchimoto1
24 Sep 1969
TL;DR: Disclosed is a method of implanting impurity ions wherein such ions are implanted into the surface of a semiconductor partially exposed by a hole in two layers, one made of silicon oxide and the other being made of a metal such as aluminum as discussed by the authors.
Abstract: Disclosed is a method of implanting impurity ions wherein such ions are implanted into the surface of a semiconductor partially exposed by a hole in two layers, one being made of silicon oxide and the other being made of a metal such as aluminum.

Patent
13 Jun 1969
TL;DR: In this article, a 0,1 to 3 micron thick electrically conducting glass layer is used to leak charge formed on the insulator to the adjacent P-type conductivity regions of the target.
Abstract: Silicon diode array vidicon targets characterized by a silicon oxide insulator disposed between P-type conductivity regions forming discrete diodes within an N-type conductivity wafer have been made substantially immune to burn-in by the utilization of a 0,1 to 3 micron thick electrically conducting glass layer to leak charge formed on the insulator to the adjacent P-type conductivity regions of the target. Preferably the electronically conducting glass is an alkaline earth metal borate glass containing an oxide of a metal, e.g., iron, vanadium, cobalt, etc., providing ions of both a higher valence state and a lower valence state within the glass to permit regulation of the resistivity of the glass layer during fabrication of the bulk glass. To inhibit crazing of the glass layer while providing superior contact between the glass and the surface of the target, the glass layer is R.F. sputter deposited atop the target employing a sputtering atmosphere, e.g., argon, nitrogen, oxygen, selected to provide the desired resistivity in the deposited glass layer.

Journal ArticleDOI
TL;DR: In this paper, it was shown that in vacuum, the maximum thermal breakdown voltage is not hampered by sparking in air and can be extended to several thousand volts, however, due to the decrease in the thermal conductance of the specimen.


Journal ArticleDOI
TL;DR: The glass-ceramics of the types examined have been shown to have high volume resistivities (greater than 108 ω cm at 500°C) and can resist the environmental conditions likely to be encountered in diffusion processes as discussed by the authors.

Patent
14 May 1969
TL;DR: In this article, a dielectric structure for semiconductor devices which provides an oxygen barrier to preserve the high charge at a silicon-silicon oxide interface, and also serves as a barrier to mobile charges in a thin film of silicon oxide.
Abstract: This invention is for a dielectric structure for semiconductor devices which provides an oxygen barrier to preserve the high charge at a silicon-silicon oxide interface, and also serves as a barrier to mobile charges in a thin film of silicon oxide. The invention also provides for a structure and method of eliminating low-voltage dielectric breakdown at the border of the active and inactive regions in a semiconductor device.