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Showing papers on "Silicon oxide published in 1983"


Journal ArticleDOI
TL;DR: In this paper, it was inferred that LPCVD oxynitrides are homogeneous on an atomic scale, i.e., the silicon atoms are randomly surrounded by oxygen and nitrogen atoms, and are therefore not to be conceived of as a physical two phase mixture of silicon oxide and silicon nitride.
Abstract: Silicon oxynitride (SiOxNy) films have been grown by a low‐pressure chemical vapor deposition (LPCVD) process from mixtures of SiH2Cl2, N2O, and NH3 at 820 °C. The overall layer composition can be varied by adjusting the N2O/NH3 gas flow ratio. Rutherford backscattering and Auger analysis of the films indicated a uniform composition throughout the layer, irrespective of the nature of the substrate. Both the thickness and the composition of these oxynitride films can conveniently be measured with ellipsometry; the oxygen to nitrogen ratio can be derived reliably from the value of the refractive index. It is inferred that LPCVD oxynitrides are homogeneous on an atomic scale, i.e., the silicon atoms are randomly surrounded by oxygen and nitrogen atoms, and are therefore not to be conceived of as a physical two phase mixture of silicon oxide and silicon nitride. Their stability in metal–oxynitride–oxide–silicon structures is found to improve with increasing oxygen content as regards flatband voltage shift upon temperature‐bias stress.

84 citations


Patent
24 Jan 1983
TL;DR: In this article, the authors describe the fusing of two silicon bodies where at least one of these bodies has a region of silicon oxide, and the bodies are contacted so that the silicon oxide is at an interface between the two bodies.
Abstract: Dielectrically isolated single crystal silicon of high quality is produced by an extremely convenient process. This process involves the fusing of two silicon bodies where at least one of these bodies has a region of silicon oxide. The bodies are contacted so that the silicon oxide is at an interface between the two bodies. The bodies are then heated to an elevated temperature while applying a nominal electrical potential across the interface. This combination of applied potential and temperature permanently fuses the two bodies without producing any significant damage to the crystal quality of these bodies.

58 citations


Patent
24 Nov 1983
TL;DR: In this paper, a method for making a dielectric isolation pattern in integrated circuit structure is described, where the layers are patterned to form openings in the structure at the areas where it is desired to form an oxide isolation pattern within the monocrystalline silicon body.
Abstract: A method for making a dielectric isolation pattern in integrated circuit structure is described. A monocrystalline silicon body (10, 20) is provided. There is formed thereon a layered structure (22, 24, 26) of silicon dioxide, polycrystalline silicon and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form an oxide isolation pattern within the monocrystalline silicon body. If it is desired to form a semi-recessed oxide isolation there will be no etching of the monocrystalline silicon body in the openings. Should it be desired to form a full recessed oxide isolation there is etching of the monocrystalline silicon to a desired depth to form a substantially planar top surface of the monocrystalline with the recessed dielectric oxide isolation. The body is then oxidized until the desired oxide isolation pattern penetrates to the desired depth within the silicon body. Through a reduced silicon oxide layer (22) and by adding the polycrystalline silicon layer (24) a substantially reduced lateral oxidation and thus smaller beak length is achieved allowing higher integration density.

49 citations


Journal ArticleDOI
TL;DR: In this paper, the rates of silicon oxide growth were analyzed in terms of both linear and parabolic coefficients, with the biggest difference seen between the linear coefficients for metallic silicides on the one hand and pure silicon on the other, with a semiconducting silicide occupying an intermediate position.
Abstract: Samples of several metal silicides grown over silicon substrates and samples of pure silicon were oxidized at the same time in an atmosphere of wet oxygen. The rates of silicon oxide growth were analyzed in terms of both linear and parabolic coefficients. The biggest difference is seen between the linear coefficients for metallic silicides on the one hand and pure silicon on the other, with a semiconducting silicide occupying an intermediate position. While the question of why metallic oxides are not always generated simultaneously with SiO2 remains a mystery, the results suggest a possible interpretation.

44 citations


Journal ArticleDOI
TL;DR: In this paper, a 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length, and the chip-select access time of the RAM was 12ns at 45mW dissipation power.
Abstract: SIMOX technology has been developed for fabricating SOI-type devices. In this technology, buried silicon oxide is used for the vertical isolation of semiconductor devices. The buried oxide is formed by oxygen-ion implantation into silicon, followed by epitaxial growth of silicon onto the surface of the residual silicon above the buried oxide. The crystallinity of the residual silicon was investigated by electron beam diffraction, while the implanted oxygen depth profile was analyzed by Rutherford backscattering spectroscopy. A 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length. The chip-select access time of the RAM was 12ns at 45mW dissi-pation power.

37 citations


Patent
Leo Dipl.-Phys. Grasser1
10 Feb 1983
TL;DR: In this article, a method for forming silicon oxide layers on silicon surfaces with at least two oxidation steps was proposed, in which a first step was performed at a low oxidation temperature (T1) in an atmosphere containing a mixture of oxygen and hydrogen chloride with a low hydrogen chloride concentration, and a second step (B3) was performed in a high oxidation temperature at a dry oxygen atmosphere.
Abstract: Method for forming silicon oxide layers on silicon surfaces with at least two oxidation steps, in which a first step (B1) is performed at a low oxidation temperature (T1) in an atmosphere containing a mixture of oxygen and hydrogen chloride with a low hydrogen chloride concentration, and in which a second step (B3) is performed at a high oxidation temperature (T2), characterized by the feature that the second step (B3) is performed in a dry oxygen atmosphere. An intermediate step (B2) may also be employed for heating from the low temperature to the high temperature.

31 citations


Journal ArticleDOI
TL;DR: In this article, a layer consisting of polycrystalline silicon and silicon oxide formed by oxygen ion implanatation was formed between the buried SiO2 and the upper Si layer, which improved characteristics for MOSFETs fabricated using SIMOX technology.
Abstract: The electric-field-shielding effect was found in a layer consisting of a mixture of polycrystalline silicon and silicon oxide formed by oxygen ion implanatation. The layer was formed between the buried SiO2 and the upper Si layer, which improved characteristics for MOSFETs fabricated using SIMOX (separation by implanted oxygen) technology. By forming this layer, the threshold voltages for the MOSFETs were almost independent of substrate bias. Drain-to-source breakdown voltages for the p-MOSFETs and n-MOSFETs were raised to 250 V and 180 V, respectively.

28 citations


Patent
15 Jun 1983
TL;DR: In this article, an electrically insulating silicon carbide sintered body was used as a substrate for a semiconductor device using a fused layer formed between a silicon oxide film formed on the surface of the sintering body and the oxide of a binder.
Abstract: high density and electrically insulating sintered body 11 has SiC as its principal component and as an electro-conductive thin layer 17 on a desired surface thereof. To achieve good bonding the electro-conductive thin layer is a metallized layer containing at least one metal selected from Group Ib and VIII metals and their alloys and a binder forming a vitreous matter with a silicon oxide, and is bonded to said sintered body via a fused layer formed between a silicon oxide film formed on the surface of said sintered body 11 and the oxide of said binder. The invention can be applied to a semiconductor device using an electrically insulating silicon carbide sintered body as the substrate.

27 citations


Journal Article
01 Jan 1983
TL;DR: In this paper, the authors conducted sliding friction experiments, X-ray photoelectron spectroscopy (XPS) analysis, and electron microscopy and diffraction studies with ferrous base metallic glasses (amorphous alloys) in contact with aluminum oxide at temperatures to 750 C in a vacuum.
Abstract: Sliding friction experiments, X-ray photoelectron spectroscopy (XPS) analysis, and electron microscopy and diffraction studies were conducted with ferrous base metallic glasses (amorphous alloys) in contact with aluminum oxide at temperatures to 750 C in a vacuum. Sliding friction experiments were also conducted in argon and air atmospheres. The results of the investigation indicate that the coefficient of friction increases with increasing temperature to 350 C in vacuum. The increase in friction is due to an increase in adhesion resulting from surface segregation of boric oxide and/or silicon oxide to the surface of the foil. Above 500 C the coefficient of friction decreased rapidly. The decrease correlates with the segregation of boron nitride to the surface. Contaminants can come from the bulk of the material to the surface upon heating and impart boric oxide and/or silicon oxide at 350 C and boron nitride above 500 C. The segregation of contaminants is responsible for the friction behavior. The amorphous alloys have superior wear resistance to crystalline 304 stainless steel. The relative concentrations of the various constituents at the surfaces of the amorphous alloys are very different from the nominal bulk compositions.

25 citations


Patent
22 Aug 1983
TL;DR: In this paper, an element region, the element isolating region and the field oxide region on the silicon substrate are formed substantially flat, and a silicon oxide insulating film is formed on the inner wall of the groove.
Abstract: A substrate structure utilized to fabricate a semiconductor device is constituted by a silicon substrate; an element region selectively formed on the silicon substrate and a relatively thick field oxide region formed adjacent to the element region; an element isolating region formed between the element region and the field oxide region, the element isolating region being in direct contact with the field oxide region; the element isolating region being provided with a relatively deep groove formed in the silicon substrate and having a relatively small width; a silicon oxide insulating film formed on the inner wall of the groove; and a silicon nitride insulating film disposed on the silicon oxide insulating film. The surfaces of the element region, the element isolating region and the field oxide region on the silicon substrate are formed substantially flat.

25 citations


Patent
29 Sep 1983
TL;DR: In this article, the authors proposed a method to prevent the source line of a thin film silicon transistor from disconnection by a method wherein line width of the overlapping region with a gate line and a polycrystalline silicon transistor is broadened than another region.
Abstract: PURPOSE:To prevent the source line of a thin film silicon transistor from disconnection by a method wherein line width of the overlapping region of the source line with a gate line and a polycrystalline silicon transistor is broadened than another region CONSTITUTION:A polycrystalline silicon thin film 15 is formed on the surface of a glass substrate 14, and the part other than the part to be formed with the drain, channel, source regions of a thin film silicon transistor is etched to be removed A silicon oxide film 16 is formed covering the surface of the polycrystalline silicon thin film 15 After a gate line 17 is formed using polycrystalline silicon doped with impurities in high concentration, an insulating film 18 is deposited on the whole of the main surface of the substrate After an ITO film 18 is formed by sputtering on the main surface of the substrate, a liquid crystal driving electrode part and a source line 22 are formed at the same time according to photoetching At this time, by broadening the width of the source line 22 only at the overlapping part with the gate line 23 and the source region 24 of a transistor, generation of disconnection is made hard even if etching is performed excessively

Patent
10 Nov 1983
TL;DR: In this article, a method of manufacturing a semiconductor device in which a layer of silicon nitride overlying a silicon oxide layer present on a substrate is etched by bringing it into contact with substantially only uncharged constituents of a plasma formed in a reactor to which a substantially oxygen-free gas or gas mixture is supplied.
Abstract: A method of manufacturing a semiconductor device in which a layer of silicon nitride overlying a silicon oxide layer present on a substrate is etched by bringing it into contact with substantially only uncharged constituents of a plasma formed in a reactor to which a substantially oxygen-free gas or gas mixture is supplied. According to the invention, 0.1 to 25% by volume of a halogen different from fluorine, or of a compound containing a halogen different from fluorine, is added to this gas or gas mixture containing fluorine or a fluorine compound. Thus, a high etching selectivity of silicon nitride with respect to silicon oxide is obtained which does not vary during etching.

Patent
26 Aug 1983
TL;DR: In this article, a method of removal of photoresist in a manufacturing process for semiconductor devices utilizes burnoff in an oxidizing atmosphere, in order to reduce contamination of underlying silicon dioxide layers, chlorine in the atmosphere getters Na+ ions, etc.
Abstract: A method of removal of photoresist in a manufacturing process for semiconductor devices utilizes burnoff in an oxidizing atmosphere. In order to reduce contamination of underlying silicon dioxide layers, chlorine in the atmosphere getters Na+ ions, etc. The chlorine gas is obtained from HCL added to the oxidizing atmosphere.

Patent
14 Jan 1983
TL;DR: In this paper, a self-aligned semiconductor device is made using two sets of superposed pattern forming layers; a master mask layer set containing the selfaligned patterns, and a pattern selector layer set which allows different apertures in the master mask layers to be selectively re-opened so that different device regions may be sequentially formed.
Abstract: Improved self-aligned semiconductor devices are made using two sets of superposed pattern forming layers; a master mask layer set containing the self-aligned patterns, and a pattern selector layer set which allows different apertures in the master mask layer to be selectively re-opened so that different device regions may be sequentially formed. The master mask layer is a double layer of a first material resistant to typical device forming processes, covered by a second etch stop material. The selector layer may be a single process resistant material or a double layer. Using combinations of silicon oxide and nitride, the process is applied to the formation of silicon islands with emitters and emitter, base, and collector contacts self-aligned to each other and a surrounding oxide isolation region. Significant area and cost savings are achieved without additional masking steps or precision alignments.

Journal ArticleDOI
TL;DR: In this article, two silicon crystals with different cooling processes were grown based upon the measured temperature profile in the growing crystal, one was quenched from about 1000°C to room temperature after termination of crystal growth.

Journal ArticleDOI
TL;DR: In this paper, the effect of Li deposition on the sputtering of Si+ from oxygenated Si surfaces has been studied and it is observed that at low oxygen coverages, the Si+ yield decreases exponentially with the Li induced decrease of the work function.
Abstract: The effect of Li deposition on the sputtering of Si+ from oxygenated Si surfaces has been studied. It is observed that at low oxygen coverages, the Si+ yield decreases exponentially with the Li induced decrease of the work function . With the formation of thermally grown silicon oxide on the surface, the Si+ yield deviates from the simple exponential dependence on . The Si+ yield becomes independent of for an appreciable range of in cases of heavier oxidation.

Patent
07 Mar 1983
TL;DR: In this article, a method for the carbothermic reduction of aluminum oxide to form an aluminum alloy including producing silicon carbide by heating a first mix of carbon and silicon oxide in a combustion reactor to an elevated temperature sufficient to produce silicon carbides at an accelerated rate, the heating being provided by an in situ combustion with oxygen gas.
Abstract: Disclosed is a method for the carbothermic reduction of aluminum oxide to form an aluminum alloy including producing silicon carbide by heating a first mix of carbon and silicon oxide in a combustion reactor to an elevated temperature sufficient to produce silicon carbide at an accelerated rate, the heating being provided by an in situ combustion with oxygen gas, and then admixing the silicon carbide with carbon and aluminum oxide to form a second mix and heating the second mix in a second reactor to an elevated metal-forming temperature sufficient to produce aluminum-silicon alloy. The prereduction step includes holding aluminum oxide substantially absent from the combustion reactor. The metal-forming step includes feeding silicon oxide in a preferred ratio with silicon carbide.

Patent
27 May 1983
TL;DR: In this paper, a zirconium oxide sintered body for an oxygen concentration sensor is produced by mixing 87.5 to 91.0% by weight of ZO powder, 8.5-12.3% of yttrium oxide powder, 0.5% of silicon oxide and 0.2 to 1.0%.
Abstract: A zirconium oxide sintered body for an oxygen concentration sensor is produced by mixing 87.5 to 91.0% by weight of zirconium oxide powder, 8.5 to 12.3% by weight of yttrium oxide powder, 0.5% by weight or less of silicon oxide and 0.2 to 1.0% by weight of aluminium oxide, drying the resulting mixture, followed by sintering so as to make the cubic phase content in crystal phase of the resulting sintered body at ordinary temperatures 95% by weight or more. Such zirconium oxide sintered bodies have excellent mechanical strength, ionic conductivity and thermal shock properties and can be used stably for a long period of time.

Patent
21 Jan 1983
TL;DR: In this article, an irradiation pattern-shaped graft polymer film is formed onto the silicon oxide film of the upper layer, and the region not coated with the graft polymer mask is removed through etching while using the graft polymeric film as a mask.
Abstract: PURPOSE:To form a pattern of a high form factor and high resolution by a small quantity of irradiation by forming a base material forming an added polymerizable active point through the irradiation of high energy rays in double- layer structure and using an organic high molecular material film as a lower layer and a silicon oxide film as an upper layer. CONSTITUTION:Base material films of two layers, the lower layer thereof consists of the organic high molecular material film and the upper layer thereof the silicon oxide film, are used, an irradiation pattern-shaped graft polymer film is formed onto the silicon oxide film of the upper layer, the silicon oxide film not coated with the graft polymer film is removed through etching while using the graft polymer film as a mask, and the organic high molecular material film in a region not coated with the silicon oxide film is removed through etching. The pattern can be transferred to the comparatively thick organic high molecular material film even when the thin silicon oxide film is used because the silicon oxide film forms the added polymerizable active point through the irradiation of high energy rays and is not etched at all through dry etching treatment using oxygen gas, an etching rate thereof is large to the organic high molecular material film.

Patent
03 Nov 1983
TL;DR: In this paper, a process for fabricating semiconductor devices including a field effect transistor was described incorporating a substrate, a layer of thermal oxide having windows, a polycrystalline silicon to form the gate electrode of field effect transistors, and a first interconnection layer, which is reflowed to smooth its upper surface over the polysilicon interconnections and to provide round edges, impurity regions formed on either side of the silicon gate electrode and bounded by the thermal oxide.
Abstract: A process for fabricating semiconductor devices including a field effect transistor has been described incorporating a substrate, a layer of thermal oxide having windows, a layer of polycrystalline silicon to form the gate electrode of field effect transistors and a first interconnection layer, a layer of silicon nitride, a layer of phosphorous doped silicon dioxide which have windows larger than the device windows and which is reflowed to smooth its upper surface over the polysilicon interconnections and to provide round edges, impurity regions formed on either side of the silicon gate electrode and bounded by the thermal oxide, forming openings to the drain and source regions, depositing a layer of metal over the substrate and defining the layer of metal to form a second layer of interconnections and also to provide ohmic contact to the source and drain regions. The process overcomes the problem of forming openings through a layer of phosphorous doped silicon oxide and further overcomes the problem of subsequent out diffusion of a drain and source impurity region at times when a layer of phosphorous doped silicon oxide is reflowed thus permitting shallow drain and source regions for short channel field effect transistors.

Patent
19 Oct 1983
TL;DR: In this article, the authors proposed a method to make interfacial characteristics excellent preventing a step disconnection from happening to make lowvoltage operation feasible by a method wherein a gate insulating film is made an insulating material continuously or discontinuously changing constituents thereof while the operational semiconductor layer junction film part thereof is made a silicon nitride film.
Abstract: PURPOSE:To make interfacial characteristics excellent preventing a step disconnection from happening to make low-voltage operation feasible by a method wherein a gate insulating film is made an insulating film continuously or discontinuously changing constituents thereof while the operational semiconductor layer junction film part thereof is made a silicon nitride film. CONSTITUTION:A transistor 1 is composed of a gate electrode 3 formed on a glass substrate 2 and a gate insulating film 7 comprising three layers, i.e. a silicon nitride layer 4, a silicon oxide layer 5, another silicon nitride layer 6 formed on the layer 3. An amorphous silicon hydride film 8 is formed on the film 7 while source.drain electrodes comprising an n amorphous silicon film 9 and an NiCr film 10 are further formed on the film 8. Besides a liquid crystal display electrode 11 provided. In such a constitution, a step disconnection may be prevented from happening without deteriorating interfacial characteristics to improve the reliability of an element since the step difference between the display electrode 11 and the source.drain electrodes 9, 10 may be minimized by means of etching said film 8 and the layer 6.

Patent
Lorenzo Faraone1
01 Sep 1983
TL;DR: In this paper, each of the silicon oxide layers insulating the conductors from each other and from the substrate surface are each individually formed by thermal oxidation so that each is tailored in thickness and electrical characteristics for the particular purpose that each serves.
Abstract: A method of making a semiconductor device having multi-levels of polycrystalline silicon conductors insulated from each other and from the silicon substrate on which the semiconductor device if formed. In this method, each of the silicon oxide layers insulating the conductors from each other and from the substrate surface are each individually formed by thermal oxidation so that each is tailored in thickness and electrical characteristics for the particular purpose that each serves.

Patent
01 Feb 1983
TL;DR: In this article, a method of fabricating CMOS integrated circuits including the ordered steps of depositing a layer of phosphorus doped silicon oxide, heating the oxide layer at a temperature and duration sufficient to reflow and densify it, forming contact apertures in the oxide layers for exposing source and drain regions of transistors, and cleaning the wafer in an etchant solution for rounding off sharp edges on the oxide surface prior to contact metallization is presented.
Abstract: A method of fabricating CMOS integrated circuits including the ordered steps of: depositing a layer of phosphorus doped silicon oxide; heating the oxide layer at a temperature and duration sufficient to reflow and densify it; forming contact apertures in the oxide layer for exposing source and drain regions of transistors; and cleaning the wafer in an etchant solution for rounding off sharp edges on the oxide layer prior to contact metallization. In a preferred embodiment, all steps between forming contact apertures and through metallization are formed at a temperature that is lower than the temperature that will cause flow of the oxide layer.

Journal ArticleDOI
TL;DR: In this article, the effect of argon ion bombardment on a silicon oxide film prepared on a Si(111) surface by dry oxidation was investigated by measuring partial yield spectra in addition to the oxygen induced Si 2p core level shift.
Abstract: The effect of argon ion bombardment on a silicon oxide film prepared on a Si(111) surface by dry oxidation was investigated by measuring partial yield spectra in addition to the oxygen induced Si 2p core level shift. The experimental observations can be understood such that the SiO2 network is decomposed at the initial stage of argon ion bombardment. In the following stage of bombardment, the silicon oxide films are sputter etched resulting in a decrease in the oxide film thickness.

Patent
Hendrik J. M. Joormann1
06 Sep 1983
TL;DR: In this article, the authors describe a glass lamp vessel that is resistant to attack by electrons, resistant to atmospheric influences and is properly workable in a gas flame, but the glass is not suitable for use in lamps.
Abstract: The invention relates to lamps having a glass lamp vessel (1) and to a glass suitable therefor. The relevant glass is adequately resistant to attack by electrons, is resistant to atmospheric influences and is properly workable in a gas flame. This glass contains 44-60 mole % silicon oxide; 0-7.5 mole % boron oxide; 0-6 mole % zirconium oxide; 0-7.5 mole % aluminium oxide; 5-20 mole % calcium oxide; 12.5-25 mole % barium oxide; 0-15 mole % magnesium oxide; 0-10 mole % strontium oxide; 2-8 mole % sodium oxide. The sum of the alkaline earth metals is 25-42.5 mole %. No discoloration occurs in sodium vapor discharge lamps when the lamp vessel has been made of this glass.

Patent
12 May 1983
TL;DR: In this paper, the N-type base layers and emitter layers are formed to the transistor forming sections, the periphery thereof are surronded by insulating isolating oxide films, extracting electrodes are formed, and the transistors of the memory cell region and the peripheral circuit region are formed.
Abstract: PURPOSE:To manufacture a large-capacitance high-speed semiconductor memory with high yield as a whole by manufacturing a transistor in a memory cell region with excellent yield and forming a transistor having high performance in a peripheral circuit region. CONSTITUTION:N Type buried layers are formed in a large number of regions as the transistor forming sections of a P type silicon substrate, and an N type silicon single crystalline layer is deposited on the surface of the substrate containing the buried layers, thus forming a composite substrate. A silicon oxide film and a silicon nitride film are formed to the surface of the substrate. Other regions are oxidized while leaving the silicon nitride film of the transistor forming sections on the buried layers in a memory cell region, and the oxide film is removed. Other regions are etched up to the depth of the silicon single crystalline layer while leaving the silicon nitride film of the transistor forming sections on the N type impurity buried layers in the peripheral circuit region except the memory cell region. Other regions in a first region and a second region are oxidized up to the P type silicon substrate. The silicon nitride film of the first region and the second region is removed through etching, P type base layers and N type emitter layers are formed to the transistor forming sections, the periphery thereof are surronded by insulating isolating oxide films, extracting electrodes are formed, and the transistors of the memory cell region and the peripheral circuit region are formed.

Patent
22 Dec 1983
TL;DR: In this article, a hydrogen-selective gas sensor comprising a gas-sensing element including a semiconductor in a principal portion thereof, and a thin coat or layer inactive for oxidation of hydrogen formed over an entire surface of the gas sensing element or at least on a surface of semiconductor.
Abstract: A hydrogen-selective gas sensor comprising a gas-sensing element including a semiconductor in a principal portion thereof, and a thin coat or layer inactive for oxidation of hydrogen formed over an entire surface of the gas-sensing element or at least on a surface of the semiconductor. The thin layer comprises one of silicon oxide, aluminium oxide, and silicon nitride, and is formed on the surface of the semiconductor by chemical deposition, the thin layer checking passage of molecules other than hydrogen molecules.

Patent
16 Dec 1983
TL;DR: In this paper, a gate electrode is used to form an electrode on shallow impurity junction layer without generation of junction breakdown by forming high concentration impurity layer on the self-alignment basis at the outside of reaction layer through impurity push-out phenomenon.
Abstract: PURPOSE:To form an electrode on shallow impurity junction layer without generation of junction breakdown by forming high concentration impurity layer on the self-alignment basis at the outside of reaction layer through impurity push-out phenomenon. CONSTITUTION:A silicon oxide film 2 for element isolation, a gate oxide film 3 and a gate electrode 4 consisting of polycrystalline silicon are formed on a silicon substrate 1, the arsenic ion is implanted under the condition that the acceleration voltage is 80keV and dose is 5X10 /cm using the gate electrode 4 as the mask, and the junction layers 5, 6 used arespectively as the source and drain are formed. Next, a Pd film is applied on the entire part of substrate in the thickness of 52nm under a substrate temperature of 250 deg.C by the vacuum-deposition method. In this case, since a substrate temperature is as high as 250 deg.C, the silicon substrate exposed at the contact hole and Pd react, forming Pd2Si layer 8 and simultaneously the arsenic ion is pushed out by the snow push phenomenon, an impurity layer 9 including a large amount of arsenic is formed at the outside of Pd2Si layer 8.

Journal ArticleDOI
TL;DR: In this paper, a high energy ion bombardment and simultaneous thin film deposition system was developed, and the results of investigations of film conductivity during formation of thin silver films on a silicon oxide substrate were presented.

Patent
12 Dec 1983
TL;DR: In this paper, the authors proposed a method to obtain excellent SiO2 film having flattening function and heat resistance in addition to reliability by using polyhydrosilsesquioxane.
Abstract: PURPOSE:To obtain excellent SiO2 film having flattening function and heat resistance in addition to reliability by a method wherein, in forming an SiO2 film for interlayer insulation to a semiconductor device, it is coated with the solution of silicon resin expressed by a specific formula, which is then heated at 350 deg.C or more. CONSTITUTION:This formation is based on a viewpoint that the use of silicon resin whose atoms or atomic groups scatter in an extremely small amount in heat treatment produces the SiO2 film having heat resistance without the decrease in flattening function after heat treatment because the reduction in volume of the scattering acid is small. In other words, when an SiOx film is formed with the silicon resin expressed by the formula, H2 is readily decomposed in thermal decomposition; therefore, the amount of impurities in the SiOx film is small, and pin holes are fine, besides the strain generated by the increase in volume due to SiO oxidation becomes small. In such a manner, polyhydrosilsesquioxane is used for preparation of SiOx films.