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Showing papers on "Silicon oxide published in 1984"


Journal ArticleDOI
TL;DR: The detailed structure of porous Si (PS) layers formed in p-type wafers with resistivities 0.01-25 Omega cm has been investigated using reflectance, transmission, ellipsometry and photoluminescence techniques as discussed by the authors.
Abstract: The detailed structure of porous Si (PS) layers formed in p-type wafers with resistivities 0.01-25 Omega cm has been investigated using reflectance, transmission, ellipsometry and photoluminescence techniques. Marked differences were observed in the optical properties of PS formed in degenerate or non-degenerate Si and these results are correlated with the results of other techniques. The optical techniques together with effective medium modelling have been shown to be useful non-destructive methods for either assessment of PS density or detection of unsuspected phases. The degenerate PS layers consistently showed good retention of the single-crystal characteristics of the starting wafer, only c-Si and voids being detected. For these samples, good agreement was obtained between optical and gravimetric densities. However, the non-degenerate PS had much greater variability, with greater loss of crystallinity and significant incorporation of oxygen, due to partial oxidation having occurred on or immediately after anodisation. Oxide fractions have been determined both optically and gravimetrically, with up to 50% oxide being detected in some samples. Non-degenerate PS samples with high oxygen concentrations appeared to be in the form of a chemical mixture, SiOx, from interpretation of the optical constants. Photoluminescence measurements together with the other techniques indicated a complex mixture of phases in the latter samples-voids, alpha -Si:O (and/or alpha -Si:H), an unknown amorphous phase and silicon oxide. This complex structure probably contributes to the observed instability of thick non-degenerate PS layers when heated in UHV as part of the cleaning procedure prior to epitaxial growth, all degenerate samples being able to withstand heat treatment.

272 citations


Journal ArticleDOI
TL;DR: In this article, it has been shown that Si(OCH3)4 is deposited irreversibly on the external surface of the mordenite crystal, thus reducing the effective size of the pore opening.
Abstract: Chemical vapour deposition (c.v.d.) of Si(OCH3)4 on the H form of mordenite has been carried out in order to control the pore-opening size without affecting its acidic properties. It has been shown that Si(OCH3)4 is deposited irreversibly on the zeolite. Because the molecular size of the alkoxide is larger than the pore size, the alkoxide does not enter the pore and the silicon compound is deposited on the external surface. The alkoxide may be deposited by reaction with hydroxide, thus covering the external surface of zeolite crystal after subsequent reactions. Calcination with oxygen removes the hydrocarbon residue and produces silica-coated H-mordenite (SiHM). The SiHM thus obtained has been characterized by temperature-programmed desorption (t.p.d.) of NH3, adsorption experiments and X-ray photoelectron spectroscopy. The deposition of the alkoxide does not change the acidity but reduces the size of pore opening. Enrichment of Si on the external surface of the zeolite is confirmed. One can therefore conclude that SiO2 covers the external surface of the zeolite, thus reducing the effective size of the pore opening. The pore size is effectively reduced by ca. 0.1 and 0.2 nm upon formation of 1–2 and 3 molecular layers of silicon oxide, respectively.

136 citations


Patent
Takeshi Okazawa1, Yoshiyuki Hirano1
28 Nov 1984
TL;DR: A metal silicide film is formed on the sides of a polycrystalline silicon layer formed on a semiconductor substrate via an insulating film, and the surface of the metal silicides film is covered by a silicon oxide film, whereby the silicon layer has a low electrical resistance and no shortcircuiting is necessary as discussed by the authors.
Abstract: A metal silicide film is formed on the sides of a polycrystalline silicon layer formed on a semiconductor substrate via an insulating film and the surface of the metal silicide film is covered by a silicon oxide film, whereby the silicon layer has a low electrical resistance and no short-circuiting is necessary. For example, in an insulated gate field effect transistor, the gate electrode is constituted by the polycrystalline silicon layer and the metal silicide film at the side walls of the polycrystalline silicon layer. Such a gate electrode has a low electrical resistance and does not cause undesirable short-circuiting with source and drain regions by the existence of the silicon oxide film formed on the surface of the metal silicide film. Also, other metal silicide film may be formed on the upper surface of the gate electrode. Moreover the silicide-SiO 2 structure may be used on the source and drain regions.

110 citations


Journal ArticleDOI
TL;DR: In this article, the authors studied thin silicon oxides of metal-oxide-semiconductor (MOS) capacitors by transmission electron microscopy and found that Fe precipitates crossing the SiO2/Si interface penetrated into the silicon oxide from the silicon substrate.
Abstract: Thin silicon oxides of metal‐oxide‐semiconductor (MOS) capacitors were studied by transmission electron microscopy. The MOS capacitors were fabricated on silicon wafers which had been intentionally contaminated by Fe+ ion implantation. It was found that Fe precipitates crossing the SiO2/Si interface penetrated into the silicon oxide from the silicon substrate. They reduced the breakdown strength by inducing singularity points in the silicon oxide.

92 citations


Patent
Shiro Hine1
25 Jun 1984
TL;DR: In this article, a selective epitaxial growth method for forming an opening, utilizing anisotropic dry etching, in a silicon oxide film formed on a silicon substrate and epitaxially growing a silicon layer selectively in the opening is presented.
Abstract: Disclosed herein is a selective epitaxial growth method for forming an opening, utilizing anisotropic dry etching, in a silicon oxide film formed on a silicon substrate and epitaxially growing a silicon layer selectively in the opening. The anisotropic dry etching is performed employing a mixed gas of carbon tetrafluoride and hydrogen, and the wall surface of the opening is perpendicular to the major surface of the silicon substrate. The epitaxial growth is achieved under a temperature of 900° to 1100° C. utilizing a mixed gas of a low pressure under 100 Torr. containing dichlorosilane as a silicon source and hydrogen as a carrier gas. A silicon layer thus obtained contains substantially no lattice defects such as a stacked fault.

71 citations


Patent
21 Dec 1984
TL;DR: Silicophosphoaluminates are crystallized from a two-phase reaction mixture comprising sources of silicon oxide, aluminum oxide, and phosphorus oxide and a suitable directing agent as mentioned in this paper.
Abstract: Silicophosphoaluminates are crystallized from a two-phase reaction mixture comprising sources of silicon oxide, aluminum oxide and phosphorus oxide and a suitable directing agent. The silicophosphoaluminates produced have ion exchange properties and are readily convertible to catalytically active material.

64 citations


Patent
15 Nov 1984
TL;DR: In this paper, the interlayers of said clay have been intercalated with three-dimensional silicon oxide pillars whereby the pillars comprise at least two silicon atom layers parallel to the clay interlayer.
Abstract: The present invention relates to intercalated clay compositions wherein the interlayers of said clay have been intercalated with three-dimensional silicon oxide pillars whereby the pillars comprise at least two silicon atom layers parallel to the clay interlayers. These materials have useful catalytic and adsorbent properties.

59 citations


Patent
Steven C. Thornquist1
20 Dec 1984
TL;DR: Silicon nitride can be etched at a rapid rate selectively against oxide in a gas plasma formed from a gas mixture comprising 10-20 parts NF 3 to 20-35 parts O 2, by volume as mentioned in this paper.
Abstract: Silicon nitride can be etched at a rapid rate selectively against oxide in a gas plasma formed from a gas mixture comprising 10-20 parts NF 3 to 20-35 parts O 2 , by volume. Silicon nitride etch rates in the range 55 to 75 milli-microns per minute are obtained at nitride/oxide etch rate ratios of 8-11:1. In contrast to the prior art methods, the invented gas system contains no carbon. Hence, deposition of carbon complexes on the substrate wafers or reactor walls during nitride etching is avoided. The NF 3 +O 2 gas mixture also etches common resists.

45 citations


Journal ArticleDOI
Alfred J. Van Roosmalen1
01 Mar 1984-Vacuum
TL;DR: In this paper, a review of recent developments in anisotropic, selective dry etching of silicon oxide over silicon is presented, together with a concise treatment on current mechanisms for etching in freon plasmas.

42 citations


Journal ArticleDOI
TL;DR: The physical properties and oxidation behavior of silicon carbide thin films were reported in this article, where these films were RF sputtered from a composite target of stoichiometric proportion onto thermally oxidized silicon substrates.
Abstract: The physical properties and oxidation behavior of silicon carbide thin films are reported. These films were RF sputtered from a composite target of stoichiometric proportion onto thermally oxidized silicon substrates. The refractive index of the carbide films, after annealing at 1100°C in hydrogen, was very close to the bulk value of 2.65. Structural and compositional properties were studied by Rutherford backscattering spectrometry, secondary ion mass spectrometry, and x‐ray diffraction techniques. Thermal oxidation was carried out in wet and dry oxygen at 900°–1100°C for a period of up to 16h. Depending on the temperature and time period, the oxidation rate of silicon carbide was about 2–11 times slower than that of single‐crystal (100) Si. The oxide layer grown out of the carbide films was determined to be silicon oxide. The average activation energy for wet and dry oxidation was calculated to be 50 and 43.5 kcal/mol, respectively. The patterning of the films was investigated using and plasmas. "Bird's beak" profiles, obtained upon field oxidation of structures, were studied.

41 citations


Patent
13 Nov 1984
TL;DR: In this article, the removal of a PSG film and the formation of an oxide film on the fuse by utilizing a manufacturing process for a capacitor in an MISFET with the fuse and the capacitor is described.
Abstract: PURPOSE:To form a hole on a fuse without increasing the number of processes by executing the removal of a PSG film and the formation of an oxide film on the fuse by utilizing a manufacturing process for a capacitor in an MISFET with the fuse and the capacitor. CONSTITUTION:A gate electrode 4 is formed in an active region in a silicon substrate 1 and an electrode 5 for a capacitor and a fuse 6 on a field oxide film 2. A source region 7 and a drain region 8 are formed, and a PSG film 9 as an inter-layer insulating film is shaped. Holes 10, 11 are formed through etching, and silicon oxide films 12, 13 are shaped through oxidation treatment. Contact holes 14, 15 are formed, Al wiring layers 16, 16a are shaped through patterning, and the capacitor C is constituted by the electrode 5, the oxide film 12 and the Al wiring layer 16a. The silicon surface of the fuse is not corroded when Si residue is removed and treated because the silicon surface is coated with the oxide film 13. An SiO2 film 17 is formed, and a hole 18 is shaped to expose one part of the fuse 6.

Patent
05 Sep 1984
TL;DR: In this article, a multi-layer of a first silicon nitride layer, a polycrystalline silicon layer, another silicon oxide layer, and a silicon dioxide layer are formed on a semiconductor body.
Abstract: A method of making semiconductor integrated circuit devices with narrow and deep isolation regions of polycrystalline silicon and wide and thick isolation regions of thermally grown silicon oxide. A multi-layer of a first silicon nitride layer, a polycrystalline silicon layer, a second silicon nitride layer and a silicon oxide layer are formed on a semiconductor body. A photoresist layer is applied on the surface of the silicon oxide layer. An opening is formed in the photoresist layer and the multi-layer. The silicon oxide layer under the photoresist layer is side-etched through the opening. The exposed polycrystalline layer is converted into another silicon oxide layer. Another opening surrounding the silicon oxide layer is formed to expose surfaces of the semiconductor body. Deep grooves are formed in the semiconductor body.

Patent
25 Jan 1984
TL;DR: In this paper, the surface of a photoelectric conversion device is covered with a silicon oxide film formed in accordance with the plasma CVD method at a temperature of less than 300° C. in an atmosphere of mixed gas consisting of silane gas and an excess of oxygen-containing gas.
Abstract: In a process for producing a photoelectric conversion device having a junction between hydrogenated amorphous silicon and an electrode made of ITO or the like, on the surface of which a passivation film made of silicon oxide is provided, the passivation film being formed by the plasma CVD method in an atmosphere of mixed gas prepared by admixing an excess of oxygen-containing gas, such as nitrous oxide, carbon dioxide, oxygen, or the like, with silane gas. The surface of the photoelectric conversion device is covered with a silicon oxide film formed in accordance with the plasma CVD method at a temperature of less than 300° C. in an atmosphere of mixed gas consisting of silane gas and an excess of oxygen-containing gas.

Patent
02 Aug 1984
TL;DR: In this paper, a laser beam is focused on an area which is shielded from the silicon substrate by the first-level conductor, so heating and disruption of the substrate or underlying circuit structure is minimized.
Abstract: A semiconductor device is programmed by a laser beam which causes an electrical short between two conductors on a silicon substrate, as by melting an insulator between the conductors and fusing or shorting the conductors. The conductors may be first and second levels of polycrystalline silicon in a standard double-level poly process, and the insulator is thermal silicon oxide. The laser beam is focused on an area which is shielded from the silicon substrate by the first-level conductor, so heating and disruption of the substrate or underlying circuit structure is minimized.

Journal ArticleDOI
TL;DR: In this paper, the structural characteristics of very thin silicon oxide films thermally grown (at 930°C, 10 Torr) in 18O enriched dry oxygen for times ranging from 0.5 to 22.5 h (corresponding to equivalent thicknesses ranging from 3.2 to 20.8 nm).
Abstract: We have studied the structural characteristics of very thin silicon oxide films thermally grown (at 930 °C, 10 Torr) in 18O enriched dry oxygen for times ranging from 0.5 to 22.5 h (corresponding to equivalent thicknesses ranging from 3.2 to 20.8 nm). Chemical etching combined with nuclear microanalysis, x‐ray photoelectron spectroscopy (XPS), and reflection high‐energy electron diffraction (RHEED) has been applied to the samples. A layer that is very slow to dissolve (of equivalent thickness ∼1.1 nm) was observed for oxide films grown for oxidation times of less than 1 h (equivalent thicknesses under 4.6 nm). As indicated by XPS this layer seems to be related to a structure different from what is observed for thicker films; its existence is also correlated to a structural order as seen by RHEED.

Patent
07 Sep 1984
TL;DR: In this paper, an anti-reflection coating for an optical component and a method of forming the same are disclosed, in which a mixture of an evaporating material and 10-30% of SiO 2 to vacuum evaporation at room temperature without heating the substrate.
Abstract: An anti-reflection coating for an optical component and a method of forming the same are disclosed. The anti-reflection coating is formed on a substrate for an optical component by subjecting a mixture of an evaporating material and 10-30% of SiO 2 to vacuum evaporation at room temperature without heating the substrate. When the anti-reflection coating is a single layer, a mixture of MgF 2 and 10-30% of SiO 2 is used as the evaporating material. When the anit-reflection coating is a multi-layer structure, a mixture of a fluoride or a silicon oxide and 10-30% of SiO 2 for a first layer, and a mixture of a fluoride or an oxide and 10-30% of SiO 2 for middle and last layers are used as the evaporating material.

Patent
19 Sep 1984
TL;DR: A thin layer magnetic head comprising a ceramic substrate consisting essentially of 100 parts by weight of a ceramic material and 0.05 to 5 parts of at least one compound from the group consisting of silicon oxide and iron oxide was proposed in this article.
Abstract: A thin layer magnetic head comprising a ceramic substrate consisting essentially of 100 parts by weight of a ceramic material and 0.05 to 5 parts by weight of at least one compound from the group consisting of silicon oxide and iron oxide.

Journal ArticleDOI
TL;DR: In this paper, a 1.3-mm film of silicon oxynitride was prepared by nitridation of silicon in a NH3/H2 plasma at a temperature of 340 °C.
Abstract: Silicon oxynitride films in the thickness range 1–6 nm have been prepared by nitridation of silicon in a NH3/H2 plasma at a temperature of 340 °C. An O/N ratio of 1.5 and a significantly smaller amount of excess silicon compared to ultrathin thermal silicon oxide films was found by Auger electron spectroscopy. Silicon oxynitride films of only 1.3 nm in thickness turned out to be good oxidation barriers up to 980 °C and revealed excellent resistance against electron irradiation. Aluminum/silicon oxynitride/p‐silicon and aluminum/silicon oxide/p‐silicon tunnel metal‐insulator‐silicon (MIS) diodes were prepared and a nearly identical I‐V behavior was observed. However, significantly increased stability of the tunnel MIS diodes with silicon oxynitride was found after life testing at 250 °C. For the two diode structures the different behavior of both series and shunt resistance during the heat treatment is discussed.

Patent
19 Nov 1984
TL;DR: In this paper, a multilayer chemical analytical element is employed for quantitative analysis of analyte in a biological fluid such as blood, consisting of a porous spreading layer, a light-blocking layer and a reagent layer on a water-impermeable light-transmissive support in order.
Abstract: A multilayer chemical analytical element is employable in quantitative analysis of analyte in a biological fluid such as blood. The element consists of a porous spreading layer, a light-blocking layer and a reagent layer on a water-impermeable light-transmissive support in order. The light-blocking layer contains a titanium dioxide fine powder with no provision of aluminum oxide compound or silicon oxide.

Journal ArticleDOI
TL;DR: In this article, the growth kinetics of thin silicon oxide films less than 300 A were studied by using a stainless steel controlled ambient oxidation system, which features resistive heating of silicon and high vacuum capability of 10−8 Torr.
Abstract: The growth kinetics of thin silicon oxide films less than 300 A are studied by using a stainless steel controlled ambient oxidation system The oxidation system features resistive heating of silicon and high vacuum capability of 10−8 Torr It is shown that the data, obtained in the oxygen pressure range of 001–05 atmosphere and in the temperature range of 930–1030 °C, can be approximated by parabolic growth law, with an activation energy of 134 eV Electrical characteristics pertinent to metal‐oxide‐semiconductor devices are also described

Journal ArticleDOI
TL;DR: In this article, the surface contamination and depth profiles of hydrogen-implanted silicon, amorphous silicon layers and silicon oxide films produced by anodic oxidation were measured by the resonant nuclear reactions1H(19F, αγ)16O and 1H(15N,αγ)12C.
Abstract: Hydrogen surface contamination and depth profiles can be measured by the resonant nuclear reactions1H(19F, αγ)16O and1H(15N, αγ)12C. The method was applied to study hydrogen-implanted silicon, amorphous silicon layers and silicon oxide films produced by anodic oxidation.

Journal ArticleDOI
TL;DR: In this article, a sliding-friction experiment was conducted with ferrous-base metallic glasses (amorphous alloys) in contact with aluminum oxide at temperatures to 750°C in a vacuum.
Abstract: Sliding-friction experiments, X-ray photoelectron spectroscopy (XPS) analysis, and electron microscopy and diffraction studies were conducted with ferrous-base metallic glasses (amorphous alloys) in contact with aluminum oxide at temperatures to 750°C in a vacuum. Sliding-friction experiments were also conducted in argon and air atmosphere. The results of the investigation indicate that the coefficient of friction increases with increasing temperature to 350°C in vacuum. The increase in friction is due to an increase in adhesion resulting from surface segregation of boric oxide and/or silicon oxide to the surface of the foil. Above 500°C, the coefficient of friction decreased rapidly. The decrease correlates with the segregation of boron nitride to the surface. Contaminants can come from the bulk of the material to the surface upon heating and impart boric oxide and/or silicon oxide at 350°C and boron nitride above 500°C. The segregation of contaminants is responsible for the friction behavior. The amorph...

Patent
L. H. Dubois1, Ralph G. Nuzzo1
29 Oct 1984
TL;DR: In the case of a clean metal surface, reaction with the silane produces an intermetallic compound that is subsequently oxidized to yield a surface layer of, for example, silicon oxide as discussed by the authors.
Abstract: Metal surfaces are protected from corrosion by reaction with a silane. In the case of a clean metal surface, reaction with the silane produces an intermetallic compound that is subsequently oxidized to yield a surface layer of, for example, silicon oxide. In the situation where the metal has an oxide coating, the silane reacts directly with this coating to produce the protective surface.

Patent
24 Sep 1984
TL;DR: In this paper, a semiconductor substrate or layer formed principally of silicon or silicon carbide is selectively or nonselectively etched by using a hydrogen fluoride gas plasma as a reactive gas plasma.
Abstract: A semiconductor substrate or layer formed principally of silicon or silicon carbide is selectively or nonselectively etched by using a hydrogen fluoride gas plasma as a reactive gas plasma. In the case of nonselectively etching the semiconductor substrate or layer, a mask layer of silicon oxide, silicon nitride, metal such as aluminum, chrominum, nickel, cobalt, tantalum, tungsten or molybdenum, or photoresist is preformed into a required pattern on the semiconductor substrate or layer.

Patent
10 Jul 1984
TL;DR: In this paper, a method for producing a-form silicon nitride (α-Si 3 N 4 ) of high-grade and fine powder for its sintered body excellent in heat-stability and mechanical strength which comprises heat-treating, in an atmosphere containing nitrogen, a mixture prepared by adding at least one of additives: (a) a mixture of Be, Mg, Ca, Sr, Ge, Sn, Ti, Hf and compounds thereof, in a total amount of 0.001 - 0.1 part by weight calculated in terms of elemental weight(
Abstract: A method for producing a-form silicon nitride (α-Si 3 N 4 ) of high-grade and fine powder for its sintered body excellent in heat-stability and mechanical strength which comprises heat-treating, in an atmosphere containing nitrogen, a mixture prepared by adding at least one of additives: (a) a mixture of at least one of Be, Mg, Ca, Sr, Ge, Sn, Ti, Hf and compounds thereof with 0.01 - 1 part by weight of silicon nitride powder, and (b) a mixture of Zr and compounds thereof with 0 - 1 part by weight of silicon nitride powder, in a total amount of 0.001 - 0.1 part by weight calculated in terms of elemental weight(s) of Be, Mg, Ca, Sr, Ge, Sn, Ti, Hf and Zr and 1 part or less by weight of silicon nitride powder, to 1 part by weight of silicon oxide powder and 0.4 - 4 parts by weight of carbon powder.

Patent
23 Aug 1984
TL;DR: In this article, a silicon film is locally etched by irradiating the fluorine source or a mixture of such fluorine sources and hydrogen sources with the light in the wavelength of 150-400nm and then placing it with silicon oxide film.
Abstract: PURPOSE:To locally etch the silicon film by irradiating a fluorine source or a mixture of such fluorine source and hydrogen source with a light of predetermined wavelength and then placing it in contact with a silicon oxide film. CONSTITUTION:A silicon film is locally etched by irradiating the fluorine source or a mixture of such fluorine source and hydrogen source with the light in the wavelength of 150-400nm and then placing it with silicon oxide film. This fluorine source should be hydrogen fluoride, C2Cl2F4, CHF2CH, SF6, XeF2, C2F6, C2F8, CHF3, CClF3, hydrogen trifluoride, carbon tetrafluoride, CBrF3, CClF2, C3ClF5, CHClF2 or silicon tetrafluoride. As a light source which generates the light, the excimer laser, Xe-H8 lamp or low pressure H8 lamp is used. Content of fluorine source in the mixture is set to 1vol% and a silicon film is locally etched.

Patent
Koji Ishida1, Hiroyoshi Matsumura1, Kenji Hiruma1, Kazuyuki Nagatsuma1, Akihito Hongo1 
26 Nov 1984
TL;DR: An optical waveguide comprising a layer formed on a substrate, having a mixed composition of silicon oxide and silicon nitride and having an arbitrary value of refractive index ranging between those of the silicon oxide.
Abstract: An optical waveguide comprising a layer formed on a substrate, having a mixed composition of silicon oxide and silicon nitride and having an arbitrary value of refractive index ranging between those of the silicon oxide and the silicon nitride. The layer of said mixed composition can be formed on the substrate to easily fabricate the optical waveguide of the present invention by conducting a sputtering method employing a Si target and controlling the composition of a sputtering gas composed of a mixture of N2 and O2 gases.

Proceedings ArticleDOI
29 Jun 1984
TL;DR: The feasibility of using a combination of ultraviolet light and ozone -UV/Ozone Cleaning - for organics removal and photoresist residue cleaning from silicon semiconductor wafers was investigated in this paper.
Abstract: The feasibility for using a combination of ultraviolet light and ozone - UV/Ozone Cleaning - for organics removal and photoresist residue cleaning from silicon semiconductor wafers was investigated. The process generates a highly oxidative atmosphere that is specific for removing trace organic residues. Product of the reactions are carbon dioxide and water. In most cases, stable inorganic materials such as oxide coatings remain unaffected. UV/Ozone exposure of silicon causes formation of a thin layer of silicon oxide that tends to retard further oxidation of the silicon. Based on the expected photochemistry o," this process, specific enhancements to accelerate the cleaning rates were tested. The enhancements involved the use of both gas phase and liquio phase additives, and comparative rates of removal were determined. The technique was tested on several photoresists, potential organic residues, and common solvent systems. The photoresists studies were primarily positive resists and were tested at several levels of ion implantation. The results of the testing suggests that the highest potential applications of UV/Ozone Cleaning in the processing of semiconductor wafers include: a) Removal of solvent residues and process contaminants. b) A pre-process step to insure cleanliness by removal of residual organic or airborne organic contaminants. c) As a post-process step to insure cleanliness or to remove trace organics.

Patent
15 May 1984
TL;DR: In this article, a mask layer 3 is formed on a substrate and an element separating groove 28 is formed by etching with the layers 3, 26 as masks, and then the layer 23 is removed, and a silicon oxide layer 29 is formed.
Abstract: PURPOSE:To readily form an insulating layer by forming a mask layer on a substrate, and then forming in a self-aligning manner an element separating insulating layer. CONSTITUTION:A mask layer 3 is formed on a substrate 1. The layer 3 has a silicon oxide layer 21, silicon nitride layers 22, 24, and a silicon oxide layer 23 added with phosphorus. Then, a mask layer 25 made of silicon nitride is formed. Subsequently, an interelement separating insulating layer 25 made of silicon oxide layer is formed. Thereafter, the layers 25, 24 are removed, and a P type impurity implanting region 27 is formed. An element separating groove 28 is formed by etching with the layers 3, 26 as masks. Then, the layer 23 is removed, and a silicon oxide layer 29 is formed. Thereafter, a silicon oxide layer 30 is formed in the groove 28.

Patent
24 Jan 1984
TL;DR: In this paper, the authors proposed to prevent a defective short circuit by electrode materials, and to inhibit the variation of threshold voltage by forming electrodes consisting of conductor layers and metals to the contact sections of source-drain in the MOS type semiconductor device and forming an electrode made of a metal on a gate.
Abstract: PURPOSE:To prevent a defective short circuit by electrode materials, and to inhibit the variation of threshold voltage by forming electrodes consisting of conductor layers and metals to the contact sections of source-drain in the MOS type semiconductor device and forming an electrode made of a metal on a gate CONSTITUTION:The source and drain regions 3 of an MOS transistor and formed on an N type silicon substrate 1 A silicon oxide film 2 on the source- drain regions 3 is removed to form contact holes 4, and a polycrystalline silicon layer 5 is formed on the substrate 1 The polycrystalline silicon layer 5 and the oxide film 2 of a gate section are removed, and a gate oxide film 6 is formed through thermal oxidation An oxide film 7 on polycrystalline silicon 5 is removed and Al is evaporated, and each electrode and wirings of the source, the drain and the gate are formed The polycrystalline silicon layer on the field oxide film 2 is removed through etching while using the Al wiring as a mask Al and polycrystalline silicon are alloyed through heat treatment, and each electrode 8, 9 and 10 of the source, the drain and the gate is formed Accordingly, the electrodes can be extracted from a shallow junction, and the variation of threshold voltage due to the coating of the gate oxide film 7 on the polycrystalline silicon layer 5 is inhibited