Showing papers on "Silicon oxide published in 1988"

CVD of silicon oxide using TEOS decomposition and in-situ planarization process

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either along or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

Inlet manifold and methods for increasing gas dissociation and for pecvd of dielectric films

Abstract: An inlet gas manifold for a vacuum deposition chamber incorporates inlet apertures which increase in diameter or cross-section transverse to the direction of gas flow. The aperture configuration increases the dissociation gases such as nitrogen and, thus increases the rate of silicon nitride deposition provided by nitrogen gas chemistry, without requiring the use of reactants such as ammonia. While one could use ammonia in the deposition gas chemistry if desired, the process provides the option of completely eliminating ammonia. The inlet manifold containing the increasing-diameter gas inlet holes provides enhanced control of the process and the deposited film, and is also useful for forming other dielectrics such as silicon oxide and silicon oxynitride. In particular, silicon oxynitride films are characterized by low hydrogen content and by compositional uniformity.

Process for PECVD of silicon oxide using TEOS decomposition

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

Selective thin film etch process

Abstract: A plasma process using a reactant gas mixture of fluorinated etching gas and oxygen for selectively etching a thin film of material such as silicon nitride with high selectivity for a silicon oxide underlayer and, preferably, for a photoresist overlayer mask.

Method of fabricating back surface point contact solar cells

Abstract: A back surface point contact silicon solar cell having improved characteristics is fabricated by hydrogenating a silicon-silicon oxide interface where hydrogen atoms are diffused through silicon nitride and silicon oxide passivating layers on the surface of a silicon substrate. In carrying out the hydrogenation, the substrate and passivation layers are placed in a hydrogen atomsphere at an elevated temperature of at least 900° C. whereby hydrogen atoms diffuse through the two passivation layers. Self-alignment techniques are employed in forming small-geometry doped regions in the surface of the silicon substrate for the p-n junctions of the solar cell. Openings are formed through the passivation layers to expose first surface areas on the substrate, and a doped silicon oxide layer is then formed over the passivation layers and on the exposed surface areas. Portions of the first doped layer on the two passivation layers are removed and then second portions of the two passivation layers are removed, thereby exposing second surface areas. A second doped silicon oxide layer is then formed over the passivation layers and on the second exposed surface areas. Dopants from the two doped silicon oxide layers are then diffused into the first and second surface layers to form p and n diffused regions in the surface of the substrate. Thereafter, the first and second doped silicon oxide layers are removed by a preferential etchant which does not remove the silicon nitride layer, thereby exposing the first and second surface areas. A two-level metal interconnect structure is then formed for separately contacting the first surface areas and the second surface areas.

Method of plasma enhanced silicon oxide deposition

Abstract: A method of depositing a hard silicon oxide based film is provided by controllably flowing a gas stream including an organosilicon compound into a plasma and depositing a silicon oxide onto a substrate while maintaining a pressure of less than about 100 microns during the depositing. The organosilicon compound is preferably combined with oxygen and helium and at least a portion of the plasma is preferably magnetically confined adjacent to a substrate during the depositing, most preferably by an unbalanced magnetron. These silicon oxide based films may be reproducibly deposited on small or large substrates, such as glass, plastic, mineral or metal, with preselected properties.

Current fluctuations and silicon oxide wear-out in metal-oxide-semiconductor tunnel diodes

Abstract: We have studied the behavior of very thin oxide (∼20 A) metal‐oxide‐semiconductor tunnel diodes under high electrical field bias. These devices do not usually experience catastrophic breakdown, but can be worn out at high fields through the creation of a low barrier tunneling path. The effective area of the path increases during stress, while the barrier height remains essentially constant at ∼1 eV. The formation of the path is correlated to the presence of multilevel switching fluctuations in the diode current. The same complex fluctuations and excess currents are seen in oxides up to 70 A where the fluctuations show up as noisy precursors to catastrophic breakdown.

Influence of the substrate on the early stage of the growth of hydrogenated amorphous silicon evidenced by kinetic ellipsometry

Abstract: Fast real‐time ellipsometry is used to study in situ, as a function of the substrate, the growth of the first tens of monolayers of hydrogenated amorphous silicon (a‐Si:H) deposited by a rf glow discharge of SiH4. The high sensitivity of this technique is illustrated and the early stage of the growth is found to strongly depend upon the nature of the substrate. A nucleation mechanism followed by incomplete coalescence is observed on metal and hydrogenated amorphous germanium (a‐Ge:H) substrates. On the contrary, fused silica (SiO2) and tin dioxide (SnO2) are superficially reduced: this reduction creates at the interface a mixed layer of a‐Si:H and silicon oxide on the silica substrate, and produces elemental tin at the surface of the SnO2 substrate. In this last case, tin is found to diffuse in the further a‐Si:H growing film. On crystalline silicon (c‐Si), the a‐Si:H growth shows incomplete coalescence followed by homogeneous growth, probably together with the reduction of the native c‐Si oxide layer.

Crystallization kinetics of amorphous Si/SiO2 superlattice structures

Abstract: Thermal annealing of amorphous silicon/silicon oxide multilayers leads to crystallization of silicon layers clad by an amorphous SiO2 matrix. Isothermal crystallization kinetics and microstructure of the crystallized layer are strongly dependent upon sub-layer thickness for a thickness less than 200 A.

Semiconductor device having a two-layer gate structure

Abstract: A semiconductor device is disclosed, which comprises source and drain regions formed in a spaced-apart relation to each other on an isolated semiconductor substrate surface, a first conductive layer formed over a channel region between the source and drain regions via a gate insulating film and serving as a floating gate electrode, a two-layer insulating layer formed on the first conductive layer and consisting of a silicon oxynitride film and a silicon oxide film, and a second conductive layer formed on the two-layer insulating layer and serving as a control gate electrode. In the semiconductor device of this structure, the silicon oxynitride film traps fewer electrons, and electrons are infrequently trapped at the time of data erasing, so that data-erasing characteristics can be improved. Further, since fewer electrons are trapped, unlike the prior art insulating layer utilizing a silicon nitride film, there is no need for providing any silicon oxide film on each side, and with the two-layer structure consisting of the silicon oxynitride film and a silicon oxide film it is possible to obtain sufficient insulation and film thickness reduction.

Laminated film having gas barrier properties

Abstract: A gas barrier laminated film comprising a thermoplastic film having a polar group and a thin silicon oxide layer formed on the one side of the thermoplastic film in which the bond energy of silicon in the silicon oxide layer varies along the direction of the thickness of the layer and becomes large in the vicinity of the plastic film. It has a high level of gas barrier properties for steam and oxygen and is suitable for a variety of packaging materials.

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent the etching of semiconductor substrate and the dry spot of substrate surface, by diffusing impurity into the anti-oxidizing film on the semiconductor substrate surface, and selectively etching the anti-oxidizing film using hydrofluoric acid. CONSTITUTION:By selectively etching a silicon nitride film 2, a silicon oxide film 4 is formed on the surface part. By impurity diffusion method applying silicon nitride, the silicon nitride film 2 and the thin silicon oxide film 4 are turned into a silicon nitride film 5 containing boron impurity and a thin silicon oxide film 6, respectively. By etching a part of the silicon nitride film 5 and the thin silicon oxide film 6 using hydrofluoric acid solution, and diffusing high concentration N-type impurity, a drain region 7 and a source region 8 are formed. After a part of a silicon oxide film 9 formed in this diffusion process is selectively etched, a gate electrode 10, a drain metal wiring layer 11 and a source metal wiring layer 12 are arranged by vapor-depositing wiring material. Thereby, the etching of semiconductor substrate and the dry spot of substrate surface can be prevented, and a transistor whose leak current and contact resistance are small, can be obtained.

Method for deposition of silicon oxide on a wafer

Abstract: A processing apparatus and method for depositing a silicon oxide layer on a temperature sensitive wafer utilizing a single process chamber provide nitrous oxide gas to the chamber with the excitation energy being provided by a remotely generated plasma while supplying silane gas in combination with illuminating the wafer with an in situ generated ultraviolet energy to produce the silicon oxide layer.

Oxidation resistant refractory coated carbon-carbon composites

Abstract: An oxygen resistant high temperature composite structure comprises a carbonous matrix and reinforcing high temperature fibers disposed within said matrix, an outer refractory coating covering said matrix, boron, in elemental form and/or as a moiety of a compound dispersed throughout said structure, silicon, in elemental form and/or as a moiety of a compound dispersed throughout said structure, and titanium, in elemental form and/or as a moiety of a compound dispersed throughout said structure, said silicon and said boron oxidizing when exposed to a high temperature, oxidizing environment to form silicon oxide and boron oxide, and said titanium forming titanium oxide which stabilizes the molten phase of the boron oxide. Microcracks which form in the refractory coating are sealed by a molten glass which forms from oxidation of the boron, silicon and titanium, thereby preventing oxidation degradation of the underlying matrix.

Optical absorption and defects in amorphous SiNx and SiOx

Abstract: Photothermal deflection spectroscopy has been used to measure optical absorption for two series of amorphous silicon-based alloys prepared by the decomposition of silane/ammonia or silane/nitrous oxide mixtures to produce a-SiNx or a-SiOx respectively. Measurements have been made in the energy range 1 to 5 e V. Each sample shows a well-defined exponential edge and a low-absorption region. The inverse slope of the exponential edge increases monotonically with nitrogen or oxygen content. The low-absorption region is analysed and discussed in terms of the defect-state density. For the silicon nitride samples the results can be interpreted in terms of silicon dangling-bond defect states. On the incorporation of some nitrogen the density of defect states increases, but the defect remains at a certain energy above the valence band edge. As stoichiometry is approached the number of such states decreases. For the silicon oxide samples, oxygen incorporation results in a decrease in the density of silicon ...

Process of forming an isolation structure

Abstract: Two thin wedges of oxide extending along and from the boundaries of the field oxide layer without solution of continuity inside the substrate for a depth such as to separate dielectrically the region of silicon, present underneath the field oxide layer, having a doping level higher than the doping level of the bulk of the substrate and the regions of oppositely doped silicon in a MOS device allow obtaining simultaneously a high threshold voltage of the parasitic transistor, a high junction breakdown voltage and an excellent immunity to "Reach-through" between the depletion regions of uncorrelated junctions together with a reduced capacitance of the junctions and an improved geometry. Such wedges of oxide are obtained by means of deep anisotropic etch of silicon through a suitably exposed area, for example by means of an overetch of the nitride used for growing the thick oxide layer according to the known technique and by the subsequent filling of the deep etch with thermally grown silicon oxide.

Composition depth profiles of oxidized silicon and sputtered GaAs from angle-resolved x-ray photoelectron spectroscopy

Abstract: An inverse Laplace transform method has been used to extract composition depth profiles from angle‐resolved x‐ray photoelectron spectroscopy data from oxidized Si and Ar+ bombarded GaAs. An iterative procedure determines a least‐squares curve fit of the data using the Laplace transforms of step functions, which are summed to yield the composition profiles. For a sample of native oxide on a Si wafer, the composition profile defines the thickness and chemical layering of the various silicon oxide states. For GaAs sputtered with 1.5‐, 3.0‐, and 5.0‐keV Ar+, the composition depth profiles show a surface composition near the bulk ratio, a subsurface As depletion, the extent of which increases with increasing ion energy, then a return to the bulk composition at greater depth. These As composition profiles result from preferential sputtering caused by surface segregation enhanced by sputter‐assisted diffusion in the near surface region.

Semiconductor memory device

Abstract: PURPOSE:To stably form a storage electrode buried type memory cell by not exposing silicon nitride contained in a capacity insulating film with a groove opening. CONSTITUTION:With silicon nitride 102 as a mask silicon oxide 103 for isolating elements is formed by thermally oxidizing on a single crystal silicon substrate 101. After a groove is formed on a capacity, a capacity insulating film made of two layers of silicon oxide 105 and silicon nitride 106 is formed on the inner wall of the groove. Then, the groove is completely buried with polycrystalline silicon 107, etched to a depth of approx. 0.5 micron from the groove opening, and the silicon nitride 106 is further removed by selectively etching to expose the silicon oxide 105 on the sidewall of the groove near the groove opening. Then, a photoresist 108 is formed on the whole surface of the substrate in which part of the groove is removed, the silicon oxide 105 is etched to expose the substrate 101 only at the part of the sidewall of the groove. Thereafter, after the photoresist 108 is removed, the groove is further completely buried with polycrystalline silicon 109.

Method of etching a layer including polysilicon

Abstract: The present invention relates to a method of forming gate lines of polycrystalline silicon, polysilicon, which may have a layer of a metal silicide thereon. The gate lines are formed over islands of silicon on an insulating substrate with the islands being covered with a layer of silicon oxide. A polysilicon layer is coated over the silicon oxide layer on the silicon island and on the adjacent surface of the substrate. Resist masking strips are formed over the area of the polysilicon layer which are to form the gate lines. The exposed area of the polysilicon layer is first plasma etched in a gaseous mixture of nitrogen, chlorine and chloroform. The chlorine etches the polysilicon and the chloroform forms a protective coating of a polymer over the side walls of the formed gate lines. The device is then subjected to a second plasma etch in a gaseous mixture of helium, chlorine and carbon dioxide. The chlorine etches away any polysilicon stringers which may extend between the gate lines along the side walls of the silicon island. The carbon dioxide provides oxygen to maintain the silicon oxide layer on the islands and carbon to maintain the polymer. Thus, any stringers which could short out the gate lines are removed without undercutting the gate lines and without removing the silicon oxide layer.

Semiconductor device with multilayer silicon oxide silicon nitride dielectric

Abstract: A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).

Manufacture of soi substrate

Abstract: PURPOSE: To perform gettering of metal ions in a semiconductor layer in which an active region is formed by making a semiconductor substrate in which the active region is formed contain chlorine ions in its cladding oxide film. CONSTITUTION: The first semiconductor substrate 1 is heated in an oxidizing atmosphere containing hydrogen chloride to form a cladding silicon oxide film 2. Cl-is taken in the oxide film 2 and it is segregated in the oxide film 2, especially in the vicinity of an interface between its film and silicon 1. A silicon oxide film 2 of the first semiconductor substrate 1 is bonded to the second semiconductor substrate 4 after putting a silicon oxide film 5 on top of the substrate 4. After that, the substrate 1 is polished from the side of the rear 3 to make its substrate thin; thus a semiconductor layer 1a in which an active region is formed is obtained on the silicon oxide films 5 and 2. Gettering of metal ions M + in the semiconductor layer 1a is performed by using Cl - segregated in the vicinity of the foregoing interface. Gettering performed in advance thus prevents the operation of a semiconductor element from being affected adversely by the metal ions M + floating in the semiconductor layer 1a. COPYRIGHT: (C)1990,JPO&Japio

Spectroscopic emission studies of O2/He and N2/He plasmas in remote plasma enhanced chemical vapor deposition

Abstract: We have analyzed He, O2 /He, and N2 /He plasmas of the remote plasma enhanced chemical vapor deposition of a‐Si:H, silicon oxide, and nitride deposition by emission optical spectroscopy and by mass spectrometry. We have detected species such as atomic N and O as well as metastable He. These will be discussed relative to the deposition of silicon nitrides, oxides, and amorphous silicon.

Semiconductor integrated circuit

Abstract: PURPOSE:To increase breakdown strength without damaging reliability and the elevation of the degree of integration by forming a trench section shaped near the lower section of the end section of a conductor layer and a conductor or an insulator formed so as to bury the inside of the trench section in a first semiconductor region between second semiconductor regions. CONSTITUTION:N-type island regions 12 are shaped to a P type silicon semiconductor substrate 11 through a buried epitaxial method. The substrate is patterned to a shape that an opening section 17 is formed between the island regions 12, an silicon oxide film 15 in a lower section and the surface of the substrate 11 are selectively removed continuously, and a trench section 18 is shaped to the surface of the substrate 11. An silicon oxide film 20 containing an impurity is deposited through a CVD method (a chemical vapor growth method). The inside of the trench section 18 is buried completely with the silicon oxide film 20 through the process. Accordingly, the film thickness of the insulating film in the lower section of a field-plate is made substantially larger than that of an silicon oxide film 19 on a flat section only by approximately the depth section of the trench section 18, thus increasing breakdown strength without forming the stepped section of the surface of the substrate.

Manufacture of semiconductor device

Abstract: PURPOSE:To form an LDD structure readily, by forming a gate electrode having an approximately trapezoidal cross section on a substrate, and implanting impurity ions with suitable energy. CONSTITUTION:A silicon oxide film 2, a polysilicon layer 3 and resist 4 are formed on a silicon substrate 1. A gate electrode 3b, which has an approximately trapezoidal cross section, is formed by isotropic etching. A gate oxide film 2a is formed by anisotropic etching. The resist 4 is removed, and ions of impurities are implanted with suitable energy by an ion implanting method. The suitable energy is referred to the energy, at which a certain amount of the impurity ions are implanted in the thin region of the electrode 3b down to the substrate 1 and the impurity ions do not penetrate the thick part of the electrode 3b. Thus a low concentration region 5 and a high concentration region 6 are formed in the surface of the silicon substrate, and an LDD structure is formed.

Si-SiO2 Interface Structures–Chemical Shifts in Si 2p Photoelectron Spectra–

Abstract: From XPS depth profiling of silicon oxide films formed on (100), (110) and (111) surfaces prepared by various oxidation processes, the effect of crystallographic orientation on the chemical shift was found, and the effects of oxidation temperature, oxidation atmosphere and annealing on the chemical shifts were found to be small. These results imply that chemical shifts are weakly affected by the change in the Si-O-Si bond angle near the Si-SiO2 interface.

Improvement of endurance to hot carrier degradation by hydrogen blocking P-SiO

Abstract: The authors report on the improvement of the hot-carrier instability of MOSFETs by putting a plasma silicon oxide (P-SiO) of specific composition between the MOSFETs and the plasma silicon nitride (P-SiN) passivation layer. The P-SiO was found to have the capability of completely blocking hydrogen diffusion and water penetration. The hydrogen-blocking effect is attributed to hydrogen trapping by the dangling bonds in P-SiO. The thickness of the P-SiO film was found to be an important factor in the blocking effect. A passivation structure with P-SiO film under P-SiN thus offers protection against hot-carrier degradation, water penetration, and chip cracking. >

Ultraviolet erasable nonvolatile semiconductor device

Abstract: An ultraviolet erasable nonvolatile seimconductor device has a floating gate, a conrol gate, and a gate insulating layer interlayered between the floating gate and the control gate. The interlayered gate insulating layer consists of three layers, a first silicon oxide layer, a silicon nitride layer layered on the first silicon oxide layer, and a second silicon oxide layer. The second silicon oxide layer as the top layer of the three-layered gate insulating layer is 30 Å or less in thickness.

Method for cleaning exhaust gases

Abstract: A method for cleaning an exhaust gas comprising a base gas and at least one toxic component selected from the group consisting of arsine, phosphine, diborane and hydrogen selenide is disclosed. The method comprises contacting the exhaust gas with a molded cleaning agent having a composition consisting essentially of (1) cupric oxide, (2) manganese dioxide, and (3) at least one metal oxide selected from the group consisting of silicon oxide, aluminum oxide and zinc oxide and having a density of from 0.6 to 1.5 g/ml, said composition having a metal atomic ratio M/(M+Cu+Mn) in the range of from 0.02 to 0.70 and a metal atomic ratio Cu/(Cu+Mn) in the range of from 0.1 to 0.9; wherein Cu represents a number of gram atom of copper; Mn represents a number of gram atom of manganese; and M represents a total number of gram atom of silicon, aluminum and/or zinc, to remove the toxic component from the exhaust gas. The method is effective even at low temperatures below 10° C.

[35] Coupling of biomolecules to silicon surfaces for use in ellipsometry and other related techniques

Abstract: Publisher Summary The formation of a biomolecular layer on a silicon surface can easily be followed by ellipsometry. This chapter presents several examples of the use of ellipsometry for the study of biomolecular interactions between receptor-cell and enzyme–coenzyme. By coupling one of the interacting components to the silicon surface the binding of the other can be monitored specifically and sometimes also quantitatively. The immobilization techniques employed all include formation of a hydrocarbon layer on top of the silicon oxide present on all silicon surfaces. By binding with established immobilization methods to this hydrocarbon layer, biomolecules, such as coenzymes, antibodies, or other active proteins can be attached to the silicon surface. The properties of the Si surface should not affect the biomolecules, leading, for instance, to denaturation, and that nonspecific adsorption which might impede any biospecific binding does not occur. The introduction of the hydrocarbon layer significantly limits nonspecific adsorption and thus protects the coupled biomolecules.