Showing papers on "Silicon oxide published in 1989"

Wafer flood polishing

Abstract: In a chem-mech polishing process for planarizing insulators such as silicon oxide and silicon nitride, a pool of slurry is utilized at a temperature between 85° F.-95° F. The slurry particulates (e.g. silica) have a hardness commensurate to the hardness of the insulator to be polished. Under these conditions, wafers can be polished at a high degree of uniformity more economically (by increasing pad lifetime), without introducing areas of locally incomplete polishing.

Silicon oxide deposition from tetraethoxysilane in a radio frequency downstream reactor: Mechanisms and step coverage

Abstract: Isotopic labeling and step coverage studies of silicon oxide deposited from tetraethoxysilane (TEOS) have been carried out by introducing TEOS(16O) downstream from an 18O2 discharge. Rutherford backscattering (RBS) data on films deposited near 440 °C show that, on average, one Si–O bond in the original TEOS molecule is preserved in the process, while mass spectrometric results indicate only H216O and C18O16O as gaseous products of the cleavage of the remaining three Si–O bonds. Infrared analyses of films deposited at room temperature show large amounts of Si–OH in a gel‐like material, and the presence of a C■O species. The results suggest a mechanism dominated by diffusion and condensation of Si–OH species that form extensive chains and preserve an Si–16O bond from the original precursor. This is followed by cross‐linking to form the final silicate network; however, Si–O bond cleavage is apparently occurring at potential cross‐linking sites via a carbonate intermediate that promotes isotopic scrambling. S...

Method of fabricating semiconductor device

Abstract: A method of fabricating a semiconductor device which includes: (1) a step of forming an opening in a silicon substrate using a first silicon oxide film and a first silicon nitride film formed on the silicon substrate as masks, (2) a step of forming a second silicon oxide film and a second silicon nitride film on the side wall of the opening by the reduced pressure CVD method and anisotropic etching method, (3) a step of performing isotropic dry etching using the first and second silicon oxide films as masks, and (4) a step of performing heat treatment in an oxidizing atmosphere using the first and second silicon nitride films as masks. Thereby, uniform isotropic etching may be accomplished by use of the dry etching method.

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce leakage current easily generated in a boundary between a P type silicon layer and a silicon oxide film by removing by etching the surface region of the P silicon layer to be easily inverted to an N-type, and forming a final silicon oxide film thereon. CONSTITUTION:Before a final oxidizing step, a surface region is etched to a depth of approx. 0.5mum, thereby removing a P type layer. A final SiO2 film 19 is formed thereon. Accordingly, in a finally obtained configuration, a boundary 12a of a p type silicon layer 12 from the film (surface protective film) 19 and its near region (boundary region) is affected by only one oxidation (final oxidation). Accordingly, the part becoming of P type does not exist. From this, even if the film 19 is formed and a reverse voltage is further applied between a p type region 15 and an n type region 18, a boundary region is hardly inverted to be of n-type, and a channel 1a is not formed. That is, the leakage current of the boundary can be sufficiently suppressed.

Deposition of silicon oxide films using alkylsilane liquid sources

Abstract: A chemical vapor deposition process for depositing silicon dioxide comprising the steps of heating a substrate upon which deposition is desired to a temperature of from about 325° C. to about 700° C. in a vacuum having a pressure of from about 0.1 to about 1.5 torr, and introducing a silane selected from the group consisting of alkylsilane, arylsilane and araylkylsilane wherein the alkyl-, aryl- or aralkyl- moiety comprises from 2-6 carbons, and oxygen or carbon dioxide into the vacuum.

Reactive magnetron sputtered zirconium oxide and zirconium silicon oxide thin films

Abstract: Thin films of ZrO2 and ZrO2–SiO2 were deposited by reactive dc magnetron sputtering. The optical properties, density, microstructure, and crystalline phase of pure ZrO2 films were found to be a function of deposition rate. In particular, the index of refraction could be varied from 1.77 to 2.13 by increasing the deposition rate from 11 to 720 A/min. The density of the films increased from 3.9 to 5.8 g/cm3 over the same deposition rate range. Small amounts of SiO2 (10 at. %) stabilized the mixed films in an amorphous phase. A linear relationship between index of refraction and SiO2 content was observed and, as in the case of pure ZrO2, increasing deposition rate resulted in mixed films with higher densities and indices for a fixed SiO2 content. The structure and optical properties of the mixed films remained unchanged with thermal cycling up to 500 °C.

Thermistor materials and elements

Abstract: A thermistor material comprising, in sintered form, (A) a matrix comprising aluminum oxide, silicon oxide, or the oxide of an element belonging to Group 2A in the Periodic Table, and (B) a conductive path forming substance comprising silicon carbide and/or boron carbide, wherein the volume ratio of silicon carbide to the matrix is up to about 1.24 is stable at elevated temperatures of 400°-800° C.

Protection of a refractory metal silicide during high-temperature processing using a dual-layer cap of silicon dioxide and silicon nitride

Abstract: A method for protecting a refractory metal silicide during high-temperature processing using a dual-layer cap of silicon oxide and silicon nitride. The problem of a silicon nitride protective layer detaching itself from an underlying refractory metal silicide layer during high-temperature processing, thus allowing tungsten atoms within the layer to oxidize, is solved by laying down a silicon oxide layer beneath the silicon nitride layer. The oxide layer acts as a mechanical stress relief layer between the refractory metal silicide and the silicon nitride layer, preventing the lifting of the nitride layer during high-temperature processing steps.

Low‐temperature deposition of silicon dioxide films from electron cyclotron resonant microwave plasmas

Abstract: Silicon dioxide films were deposited on crystalline silicon substrates by electron cyclotron resonant (ECR) microwave plasma‐enhanced chemical vapor deposition (PECVD). Films were grown on Si〈100〉 substrates at temperatures of 140–600 °C, flow rates of 0.5–10 sccm SiH4, 10–30 sccm O2, and at a pressure of 10−3 Torr. Infrared absorption spectroscopy of the samples indicated no detectable SiH, OH, or SiOH groups. Neither an afterglow chemistry nor He dilution was required to eliminate H impurities as was previously reported for silicon oxide films deposited from rf plasmas. This suggests that significant differences exist between rf and ECR microwave plasma chemistries. We have found that the stoichiometry and index of refraction was not sensitive to oxidant ratio for a wide range of conditions in contrast to other studies. Stoichiometric SiO2 films, with good physical properties, were grown for a much wider range of oxidant ratios relative to those which are characteristic of the rf PECVD technique. In add...

Infrared spectroscopic ellipsometry using a Fourier transform infrared spectrometer: some applications in thin-film characterization

Abstract: The prototype of an infrared spectroscopic ellipsometer using a Fourier transform PC‐based infrared spectrometer is described. Several applications in thin‐film characterization are given, particularly in the case of bulk substrate, thick‐layered materials, and determination of the dielectric function of layered materials such as silicon oxide and silicon nitride. The sensitivity and possible improvements of this technique are discussed.

Semiconductor device with insulating isolation groove

Abstract: A semiconductor device comprising an insulating isolation groove which comprises a groove in a substrate, an insulating film on the inner surface of the groove, a polycrystal silicon film and a boron phosphosilicate glass film in order embedded within the groove, and a silicon oxide film on the boron phosphosilicate glass film. Since the polycrystal silicon film and boron phosphosilicate glass film are embedded within the groove, the crystal defect due to thermal expansion does not occur. And, since it is not necessary to oxidize the surface of the polycrystal silicon film within the groove, deformation due to an increased build-up at the time of oxidation does not occur.

Process for manufacturing a semiconductor device

Abstract: A process for the fabrication of CMOS devices is disclosed in which a selectively doped silicon layer is selectively oxidized to provide a differential thickness in the silicon and in the overlaying silicon oxide. In accordance with one embodiment, a semiconductor substrate is provided having a layer of silicon overlaying a surface of that substrate. A first area of the layer of silicon is selectively doped with N-type impurities while a second area is left undoped. The silicon is thermally oxidized to form a thermal oxide having a greater thickness over the N-type doped area than over the undoped area. Correspondingly, the silicon under the thick thermal oxide has a lesser thickness than the silicon under the thin thermal oxide. The layer of silicon is patterned to form gate electrodes and interconnects, with some of the gate electrodes formed from the silicon having N-type dopant and some of the gate electrodes formed from the silicon which is not doped N-type. Sidewall spacers are formed at the edges of the gate electrodes by anisotropically etching a sidewall spacer forming material. Because of the differential thickness of the gate electrode structures, the spacers at the edges of the N-type doped gate electrodes will be of a different thickness than are the sidewall spacers at the edges of the silicon gates not having the N-type doping. The sidewall spacers of different width are, in turn, used as a dopant mask for the formation of doped regions within the surface of the semiconductor substrate. The disclosed process allows independent doping of the polycrystalline silicon and the semiconductor substrate. A high doping concentration in the polycrystalline silicon helps to minimize the diffusing of dopant through a metal silicide layer formed on the polycrystalline silicon.

Method of making cmos with shallow source and drain junctions

Abstract: A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer. The silicide region over each of the well regions is doped with a conductivity modifier of a conductivity type opposite that of the well region. The device is then heated to diffuse the conductivity modifiers through the polycrystalline silicon layer into the silicon body to form shallow source and drain regions in each well at each side of the gate lines.

Method of making a MOS transistor

Abstract: A method of making a MOS transistor having source and drain extensions includes forming on a surface of a substrate of single crystalline silicon a gate line having a thin layer of silicon oxide between the gate line and the substrate surface. A light dose of ions of a desired conductivity type are embedded in the substrate surface at each side of the gate line up to the side walls of the gate line. Spacers of thermally grown silicon oxide are formed on the side walls of the gate line and a dose of the ions of the desired conductivity type are embedded into the substrate surface at each side of the gate line to form source and drain regions. The source and drain regions extend up to the spacers and have lightly doped extensions extending up to the side walls of the gate line under the spacers.

Method for fabricating a silicon force transducer

Abstract: A silicon substrate (112) having {100} nominal crystalline planes is anisotropically etched to form a pair of V-shaped grooves (18,20) along the top planar surface (14) and a first plate (16) between the grooves. The top planar surface is then doped to form a conductor region including the first plate 16). A substantially uniform layer (26) of a selectively etchable material, such as silicon oxide, is then grown over the grooved top planar surface. A layer (24) of doped silicon is grown over the silicon oxide layer to define a pair of V-shaped members opposite the pair of grooves. The silicon layer (24) is then partially etched to form a second plate (22) connected to the silicon layer (24) through a pair of V-shaped members (28,30). Both the second plate (22) and the pair of V-shaped members (28,30) are then suspended over the first capacitive plate (16) by etching a portion of the selectively etchable layer(26). Electronic circuitry (32) is then coupled to both the doped silicon layer and the doped substrate to detect changes in capacitance between the first and second plates (16,22) in response to an applied force, such as airflow, to be measured.

The electrical properties of copper phthalocyanine thin films using indium electrodes

Abstract: A systematic study has been made of DC electrical conduction processes through evaporated copper phthalocyanine thin films with indium electrodes. Samples showed asymmetric conductivity, which was attributed to tunnelling effects at the interface with the injecting electrode under forward bias and to trap-dominated space-charge-limited conduction under reverse bias. For tunnelling the barrier height was estimated to be approximately 0.3 eV, while the traps were exponentially distributed in energy and of concentration approximately 1024 m-3. The temperature parameter characterising the exponential trap distribution was sensitive to the deposition conditions and the sample structure, yielding typical values of 1421 K for simple sandwich structures and 781 K for samples with edge-thickening silicon oxide layers. The difference between the two values was attributed to the evolution of oxygen during deposition of the additional layer. Four-layer samples, which included an additional silicon oxide layer between the electrodes, showed considerably reduced conductivity which was attributed to Poole-Frankel emission with a field-lowering coefficient of value 1.95*10-5 eV m1/2 V-1/2.

Evidence for the defect pool concept for Si dangling bond states in a-Si:H from experiments with thin film transistors

Abstract: We compare the characteristics of a-Si:H TFTs made using silicon nitride and silicon oxide gate insulators, and then determine the energy distribution of states in the amorphous silicon band -gap. We also subject the transistors to positive and negative bias-stress, which creates new states in the gap. We find the majority of intrinsic deep states occur at a higher energy for oxide transistors than for nitride transistors. We also find that the metastable states induced by positive bias-stress occur at a higher energy than those induced by negative bias-stress. The results are consistent with the defect pool model for the Si dangling bond states.

Stability of hydrogen in silicon nitride films deposited by low‐pressure and plasma enhanced chemical vapor deposition techniques

Abstract: Hydrogen concentration depth profiles in silicon nitride films deposited by low‐pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD) techniques were studied. Quantitative hydrogen profiling was carried out using the resonant nuclear reaction 15N+1H→12C+4He+γ ray. Hydrogen concentration in as‐deposited LPCVD silicon nitride films was ∼2.5×1021 atoms/cm3 and was stable even after a furnace anneal at 450 °C in 3% H2/Ar for 30 min or a rapid thermal anneal at 1000 °C in oxygen for 30 s. These nitride films thus appear to be good hydrogen diffusion barriers. In contrast, hydrogen concentration in as‐deposited PECVD silicon nitride films was ∼1.75×1022 atoms/cm3 and dropped to ∼7.5×1021 atoms/cm3 after rapid thermal annealing at 1000 °C in oxygen for 30 s. During high‐temperature anneals, the hydrogen diffused from PECVD silicon nitride film into the underlying SiO2 layer. A comparison of the hydrogen concentration in these deposited oxides under the nitrides with those previously reported for as‐deposited, but uncovered, SiO2 films points out that the observed threshold voltage shifts in nitride covered metal–oxide semiconductor capacitors are related to the loss of hydrogen from the silicon oxide during vacuum processing for nitride deposition and to the subsequent diffusion in SiO2 from the PECVD nitride films.

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce cost by forming a process, wherein a well region in which a bipolar transistor is shaped and another well region in which a MOS transistor is formed, are shaped by one-time photolithographic process. CONSTITUTION:An silicon oxide film 2, an silicon nitride film 3 and an silicon oxide film 4 are formed successively onto a P-type semiconductor substrate 1, and a region, in which a P-type buried layer 6 is shaped, in the oxide film 4 is removed. Boron is ion-implanted to form the P-type buried layer 6, and the oxide film 4 is etched and an opening section is expanded only by a specified quantity. The nitride film 3 is etched, using the oxide film 4 as a mask, and the oxide film 4 is removed. A silicon oxide film 8 is shaped through oxidation, employing the nitride film 3 as a mask, and the nitride film 3 is removed. Arsenic ions are implanted to form an N-type buried layer 7. An n-type epitaxial layer 9 is shaped onto the whole surface of the substrate, then a P-type well 10 is formed through the same method as the P-type buried layer 6. N-type wells 11a, 11b are shaped through the same method as the N-type buried layer 7, and a region 15 and an electrode 13 are formed onto the region 10. A region 17 is shaped onto a base region 16 in the N-type well region 11a, and a region 12 and an electrode 13 are formed onto the region 11b. Accordingly, manufacturing processes are decreased, thus reducing cost.

Embedded isolation region and process for forming the same on silicon substrate

Abstract: An embedded isolation region and a process for forming the same on the substrate made of silicon. The isolation region(s) is constituted of a silicon nitride region, a silicon oxide region and, if required, a channel stop region in this order in the upper surface of the substrate to the deep inside of the substrate. The isolation region(s) is formed by an ion implantation technique using a mask made of an oxide film, followed by oxidation and removal of at least an upper substrate region on the upper side of the silicon nitride region. As compared with the formation of a conventional trench type region(s), even isolation regions with different sizes or an isolation region having portions with different sizes can be formed without a fear of entailing an uneven surface, and the development of crystal defects can be mitigated without an increase in the number of steps, while, even in a trench filled with poly-Si, at the same time some adverse effect of the remaining poly-Si on element regions can be avoided.

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To miniaturize a polycrystalline silicon film and to easily obtain insulation at the time of high temperature by selectively implanting predetermined ions of oxygen or the like to the polycrystalline silicon film to enhance the resistance of a nondiffused section. CONSTITUTION:An insulating substrate 10 is made of a single-crystal silicon substrate having a thermal silicon oxide film 112 having approx. 0.5mum of thickness on one main surface. A recess 116 is formed on one main surface of its opposite side, and its thinned section forms a diaphragm 117. Regions 12, 13, 14 are formed on a polycrystalline silicon film 11. The polycrystalline silicon piezoresistance element region 12 and the polycrystalline silicon output wiring region 13 are of dopant-diffused P and P type regions having approx. 0.5mum of thickness, and formed at predetermined positions on the film 112. The high resistance region 14 is of a nondoped nondiffused section. This region 14 is formed with a mask for selectively implanting oxygen ions on the film 11, and formed by removing the mask after the ions are implanted.

Manufacture of semiconductor device

Abstract: PURPOSE:To shorten an emitter annealing time and to reduce the movement of a base depth by forming a polycrystalline silicon for an emitter extraction electrode by heat treating an amorphous silicon film. CONSTITUTION:After an opening is formed in an element forming region, a polycrystalline silicon 7 for a base extraction electrode to which a P-type impurity is introduced is formed, an emitter forming region is opened, and a base 6 is formed by heat treating and P-type impurity ion implanting. Then, after a silicon oxide film 10 is formed on a whole surface, an emitter forming region is again opened. Thereafter, a non-doped amorphous silicon film is grown by a reduced pressure chemical vapor growing unit on the emitter forming region with SiH4 as a material gas, and arsenic is ion-implanted. Then, it is lamp annealed at 1000 deg.C, an emitter 8 is formed, with the amorphous silicon film as a polycrystalline silicon film, patterned to form an emitter leading electrode 9. Further, after an opening is formed in the film 10, wirings 11 are formed.

An investigation of the roughening of silicon(100) surfaces in Cl2 reactive ion etching plasmas by in situ ellipsometry and quadrupole mass spectrometry

Abstract: The conditions which cause silicon roughening in Cl2 RIE plasmas are investigated. I n s i t uellipsometry provides a quantitative interpretation of the extent and nature of the roughening process, while mass spectrometry yields complementary information regarding the composition of the plasma. The degree of roughening is reproducible when base pressures are ≊10−5 Torr but is strongly dependent on the rf power and process pressure. Careful selection of these parameters (50 W, 100 mTorr) retains a smooth siliconsurface and gradually smooths those which have been roughened. Water vapor has a very significant effect on the etching reactions. In low concentrations it induces roughening and in high concentrations it prevents any etching of silicon. We suggest that silicon oxide micromasks are not responsible for roughening. Instead we propose that hydroxyl (SiOH) groups are the more likely masking species. Roughening of silicon is efficiently prevented when the wafer is patterned with positive photoresist. It is possible that CCl x (x=1–4) species can remove the micromasks to retain a smooth surface.

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent a short circuit between a chip and a wire when an edge touch is caused by a method wherein a wafer is irradiated with a laser beam in a high-concentration oxygen atmosphere during a dicing operation in order to form a highly insulating oxide film at an edge of the chip simultaneously with the dicing operation CONSTITUTION:A groove 1 is worked in a wafer by means of a laser beam in a high-concentration oxygen atmosphere of 80% or higher of oxygen and 20% of an inert gas A silicon oxide film 2 is formed to be 2-4mum thick as a silicon oxide film after silicon has been melted during formation of the groove 1 has taken oxygen in high-concentration oxygen as an ambient atmosphere A substrate 3 is a silicon wafer substrate The groove 1 for chip cutting use is formed in the wafer; a silicon oxide film 10 used to prevent a wire from coming into electrical contact with a chip when the wire is slackened during a wire bonding operation or after the wire bonding operation can be formed simultaneously; a complicated operation to correct the wire or the like during an assembly process can be omitted; a semiconductor device of high reliability can thus be supplied

Directional deposition of dielectric silicon oxide by plasma enhanced TEOS process

Abstract: A description is given of the deposition of dielectric silicon oxide from TEOS in helium/oxygen mixtures in a parallel-plate RF plasma reactor. Under appropriate process conditions, highly directional deposition of low-stress stoichiometric silicon oxide is achieved. The step coverage profiles and the chemical and physical properties of these SiO/sub 2/ films were studied to gain an understanding of the origin of preferentially vertical deposition. The typical deposition conditions used in this study were 1 torr total pressure, 320 degrees C substrate temperature, 1-40% TEOS, and 0-80% O/sub 2/ in low-power-density (0.1-0.4 W/cm/sup 2/) 14 MHz RF discharges. Step coverage, chemical stability and film stress were found to be most dependent on the O/sub 2/:TEOS gas flow ratio. This dependence can be explained by the various effects involved in the oxide deposition mechanism. >

Manufacture of semiconductor device

Abstract: PURPOSE:To properly perform etching back by covering the upper and lower layer wiring of a substrate with an insulating film, and, in flattening the surface of an applied insulating film, performing etching back of the applied insulating film by forming a film of a transmissivity different from the applied insulating film on the insulating film and while observing under an optical microscope. CONSTITUTION:A lower layer wiring 2 is formed on a silicon wafer 1, a silicon oxide film 3 is laminated thereon, thin alumina 4 as an insulating film of lower transmissivity than an applied insulating film 5 is laminated and coated with said applied insulating film 5, and etching back of the applied insulating film 5 is performed to eliminate the applied insulating film 5 except that on the silicon oxide film 3 and in the depression of alumina 4. It is judged from the difference in transmissivity between alumina 4 and the applied insulating film 5 and by surface observation under an optical microscope whether or not the applied insulating film 5 which must be eliminated remains. And then a second silicon oxide film 6 is laminated and through holes 7 are formed. This facilitates the proper judgement of the end of the etching back by using the difference in transmissivity.