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Showing papers on "Silicon oxide published in 1991"


Journal ArticleDOI
TL;DR: In this article, 3-Aminopropyl triethoxy silane (APTES) was deposited onto silicon oxide surfaces under various conditions of solvent, heat, and time, and then exposed to different curing environments, including air, heat and ethanol.

553 citations


Patent
19 Dec 1991
TL;DR: In this article, the authors describe a process for forming a silicon oxide film comprising the step of depositing a thin film of a silanol, a polymer thereof or a siloxane polymer, each containing an organic group, on a substrate by exciting a gas containing an organosilane or organosILoxane gas and a gas contained H and OH on the substrate in a reaction chamber to cause a reaction in a gas phase or on the substrates and removing the organic group from the thin film by plasma treatment.
Abstract: A process for forming a silicon oxide film comprising the step of depositing a thin film of a silanol, a polymer thereof or a siloxane polymer, each containing an organic group, on a substrate by exciting a gas containing an organosilane or organosiloxane gas and a gas containing H and OH on a substrate in a reaction chamber to cause a reaction in a gas phase or on the substrate and the step of removing the organic group from the thin film by plasma treatment. Preferably the thin film is formed by repeating the depositing step and the removing step in the same chamber and is heat treated at a temperature of 450 °C or below. This process provides a good insulation film having a flatness comparable to that of an SOG film.

358 citations


Patent
Masazumi Matsuura1
25 Oct 1991
TL;DR: In this paper, a method of manufacturing a semiconductor device having a flat surface and an interlayer insulating film having superior crack resistance is disclosed, where a first silicon oxide film having a superior step coverage is deposited on the above-mentioned first Silicon oxide film so as to fill the recessed portions of a stepped pattern and to cover said stepped pattern.
Abstract: A method of manufacturing a semiconductor device having a flat surface and an interlayer insulating film having superior crack resistance is disclosed. A first silicon oxide film having a superior crack resistance is formed on a semiconductor substrate so as to cover the surface of a stepped pattern. A second silicon oxide film having a superior step coverage is deposited on the above-mentioned first silicon oxide film so as to fill the recessed portions of said stepped pattern and to cover said stepped pattern. The above-described second silicon oxide film is etched to a prescribed thickness. A third silicon oxide film superior in filling of recesses is placed into the recessed portions existing on the surface of the above-described second silicon oxide film after its etching. A fourth silicon oxide film is formed on said semiconductor substrate including the above-described second silicon oxide film and third silicon oxide film.

192 citations


Patent
30 Jul 1991
TL;DR: In this paper, a process for preparing high-step coverage silicon dioxide coatings on semiconductor wafers comprising the placing of the wafer to be coated in a process chamber, introducing disilane and nitrous oxide into the process chamber and maintaining wafer in an atmosphere consisting essentially of a gaseous mixture of disileane and Nitrous oxide and initiating and maintaining plasma enhanced chemical vacuum deposition of silicon dioxide from said gaseus mixture by applying radio frequency energy to the Wafer to create a plasma adjacent the surface of said wafer is disclosed.
Abstract: A process for preparing high step coverage silicon dioxide coatings on semiconductor wafers comprising the placing of the wafer to be coated in a process chamber, introducing disilane and nitrous oxide into the process chamber and maintaining the wafer in an atmosphere consisting essentially of a gaseous mixture of disilane and nitrous oxide and initiating and maintaining plasma enhanced chemical vacuum deposition of silicon dioxide from said gaseous mixture by applying radio frequency energy to the wafer to create a plasma adjacent the surface of said wafer is disclosed.

167 citations


Patent
20 Dec 1991
TL;DR: In this article, the structural body of a ferroelectric capacitor C is located over a source region (23) between a gate electrode (22) and a local oxide film (26).
Abstract: The structural body of a ferroelectric capacitor C is located over a source region (23) between a gate electrode (22) and a local oxide film (26). The structural body has a ferroelectric film (29) and an upper electrode (30) and a lower electrode (31) for sandwiching the ferroelectric film (29), and is provided with a conductive oxide film (32) between the lower electrode (31) and the source region (23). The conductive oxide film (32) is ITO, ReO 2 , RuO 2 or MoO 3 . If an oxygen anneal is conducted after forming the ferroelectric film (29) for the purpose of reforming crystallizability of the ferroelectric film (29), oxygen enters into the conductive oxide film (32) to some extent. As a result, the conductive oxide film (32) is further oxidized, and becomes a so-called oxide barrier or dummy layer. Therefore, formation of a silicon oxide film hardly occurs on the source interface, reduction of contact resistance and avoidance of series parasitic capacitance can be attained, the degree of freedom of the capacitor C forming region is increased, and a high density integration can be schemed.

90 citations


Patent
05 Feb 1991
TL;DR: In this article, a silicon oxide film is formed on a substrate by sputtering, which is carried out at a low temperature to prevent fixed electric charges from being generated in the film and to obtain an oxide film of good properties, the proportion of argon is adjusted to 20% or less.
Abstract: A method of forming an oxide film and a method of manufacturing an electronic device utilizing the oxide film is disclosed. A silicon oxide film is formed on a substrate by sputtering. Therefore, the film formation is carried out at a low temperature. The sputtering atmosphere comprises an oxidizing gas and an inert gas such as argon. In order to prevent fixed electric charges from being generated in the film and to obtain an oxide film of good properties, the proportion of argon is adjusted to 20% or less. Alternatively, a gas including halogen elements such as fluorine is added to the above sputtering atmosphere at a proportion less than 20%. Hereupon, alkali ions and dangling bonds of silicon in the oxide film are neutralized by the halogen elements, whereby a fine oxide film is obtained.

87 citations


Journal ArticleDOI
TL;DR: In this article, a new processing sequence involving the removal of thermal oxide by buffered HF (pH=5), followed by etching in a 40% ammonium-fluoride solution, produces a remarkably homogeneous H/Si(111)•(1×1) surface, characterized by a 0.05 cm−1 broad Si•H stretch mode.
Abstract: Infrared reflection‐absorption measurements of the Si‐H stretching vibrations of HF‐etched Si(111) surfaces show that the structure of the H‐passivated surfaces depends strongly on the nature of the initial silicon‐oxide layer. For similar etching conditions, thermal oxides lead to much flatter surfaces than chemical oxides. A new processing sequence involving the removal of thermal oxide by buffered HF (pH=5), followed by etching in a 40% ammonium‐fluoride solution, produces a remarkably homogeneous H/Si(111)‐(1×1) surface, characterized by a 0.05 cm−1 broad Si‐H stretch‐mode.

79 citations


Patent
23 Jan 1991
TL;DR: In this paper, a high pressure, high throughput, single wafer, semiconductor processing reactor is described which is capable of thermal CVD, plasma-enhanced CVD and plasma assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

75 citations


Patent
05 Jul 1991
TL;DR: In this article, an oxide film is provided on the side of a wiring conductive film providing on the upper part of field oxide films and a gate electrode, while an insulating film is required on the sides of opening parts for contact.
Abstract: PURPOSE:To enhance the reliability by a method wherein an oxide film is provided on the side of a wiring conductive film provided on the upper part of field oxide films and a gate electrode while an insulating film is provided on the sides of opening parts for contact. CONSTITUTION:Field oxide films 2 are selectively provided on a P type Si substrate 1; a gate oxide film 3 is provided on the surface of the films 2; and B ions are implanted in the substrate 1 using the films 2 as masks. Next, a silicon oxide film 5 is deposited on the surface to selectively form a gate electrode 4 while P ions are implanted using the electrode 4 and the films 2 as masks to form N-type diffused regions 6. Another silicon oxide film 7 is deposited on the surface; arsenic ions are implanted in the substrate 1 leaving the film 7 only on the sidewall part of the electrode 4; N type diffused region 8 connecting to the region 6 are formed and then the other silicon oxide film 9 is deposited on the whole surface. Finally, a polycrystal Si film 10 is deposited on the whole surface and after reflowing process to flatten the surface, the films 10, 12 in the opening part 13 formed by processing a photoresist film 12 coated on the whole surface are removed and then the other silicon oxide film 4 is deposited to form electrode wirings 15. Through these procedures, the insulation between the wirings 15 and the conductive films as well as the reliability can be enhanced.

75 citations


Patent
16 Jul 1991
TL;DR: In this article, a two-layer nonvolatile semiconductor memory device with a four-layer interlayer insulating film is presented. And the threshold voltage of the device is stabilized even after data-erase operation.
Abstract: In a nonvolatile semiconductor memory device with a two-layer gate structure, an interlayer insulating film is formed on a floating gate electrode of, e.g., polycrystalline silicon. The interlayer insulating film has a four-layer structure in which a first silicon nitride film, a first silicon oxide film, a second silicon nitride film and a second silicon oxide film are laminated in this order on the floating gate electrode, or a two-layer structure in which a first silicon nitride film and a first silicon oxide film are laminated in this order on the floating gate electrode. With the above structure, the threshold voltage of the semiconductor device is stabilized even after data-erase operation. Since, moreover, the first silicon oxide film can be formed by oxidizing the first silicon nitride film, then the quality of the first silicon oxide film can be enhanced, and accordingly the charge retaining properties of the device can be increased.

73 citations


Patent
28 Aug 1991
TL;DR: In this paper, a method of manufacturing a thin film transistor having a low leakage current including depositing a layer of silicon oxide on a semiconductor substrate, forming islands in this polysilicon layer, forming a gate oxide layer on one of the islands by oxidizing the island under high pressure at a temperature below 650° C.
Abstract: A method of manufacturing a thin film transistor having a low leakage current including depositing a layer of silicon oxide on a semiconductor substrate or on a layer of silicon nitrate deposited on a glass substrate, depositing a polysilicon layer, at a temperature of 520°-570° C., on the silicon oxide layer, annealing this polysilicon layer in a nitrogen atmosphere at a temperature of less than 650° C., forming islands in this polysilicon layer, forming a gate oxide layer on one of the islands by oxidizing the island under high pressure at a temperature below 650° C., forming a gate from a heavily doped polysilicon layer deposited on the gate oxide layer, forming lightly doped source and drain areas laterally adjacent to the gate, providing a thin layer of silicon oxide on the gate and the source and drain access, heavily doping areas of the first silicon layer adjacent to the source and drain areas, annealing the source and drain areas at a temperature below 650° C. and hydrogenating the resistive transistor with a hydrogen plasma.

Patent
07 Nov 1991
TL;DR: In this paper, the process comprises the sequential formation, on a silicon substrate (1), of a lower layer (2), of silicon oxide, of an intermediate layer (3) of silicon nitride and of an upper layer (4, 15) of polycrystalline silicon, followed by the etching of the latter for the definition of a window having a width greater than that of the desired trench (8).
Abstract: The process comprises the sequential formation, on a silicon substrate (1), of a lower layer (2) of silicon oxide, of an intermediate layer (3) of silicon nitride and of an upper layer (4, 15) of polycrystalline silicon or of silicon oxide, followed by the etching of the latter for the definition of a window (5, 16) having a width greater than that of the desired trench (8). The window (5, 16) is then narrowed down to the width of the desired trench (8) accomplishing some spacers (11) or oxidizing the layer of polycrystalline silicon (15). There is then executed the etching of the substrate (1) inside said narrow window (7, 14, 18) for the accomplishment of the trench (8), followed by the oxidation of the walls of the trench (8) and by its selfplanarization.

Patent
15 Jul 1991
TL;DR: In this article, the authors proposed a method to obtain a selection ratio nearly equal to the one in the case where a silicon oxide film is used as mask material, by previously adding organic material having unsaturated bonds to etching gas.
Abstract: PURPOSE:To obtain a selection ratio nearly equal to the one in the case where a silicon oxide film is used as mask material, by previously adding organic material having unsaturated bonds to etching gas. CONSTITUTION:When dry etching is performed, in order to form contact holes and the like with a reactive ion etching equipment, by using a silicon oxide film as a mask, MMA (methacrylate methyl) being organic material having unsaturated bonds is added to etching gas. The organic material produces a polymerized film preventing the etching of substrate silicon, on the substrate silicon. Hence the decrease of the selection ratio of the silicon oxide film to the substrate silicon is avoided, and further the hole diameter dependency of the selection ratio can be decreased.

Patent
15 Nov 1991
TL;DR: In this article, a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600°C.
Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600° C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.

Patent
20 Aug 1991
TL;DR: In this article, a method for forming thin, suspended membranes of epitaxial silicon material is described, which is suitable for use as diaphragms and microbridges in a microaccelerometers or a pressure sensor.
Abstract: A method is disclosed for forming thin, suspended membranes of epitaxial silicon material. Silicon oxide strips (12) having a predetermined thickness are first formed on a silicon substrate (10). A gap (14) provided between adjacent pairs of strips (12) is preferably less than or equal to about 1.4 times the thickness of the silicon oxide strips (12). The underlying silicon substrate (10) is exposed within these gaps (14) in the silicon oxide layer, whereby the gaps (14) provide seed holes for subsequent epitaxial growth from the silicon substrate (10). Epitaxial silicon is grown through the gaps (14) and then allowed to grow laterally over the silicon oxide strips (12) to form a continuous layer (20) of epitaxial silicon over the silicon oxide strips (12). The backside of the silicon substrate (10), i.e., the surface opposite the surface having the silicon oxide strips (12), is then masked to delineate the desired diaphragm and microbridge pattern. The silicon is etched conventionally from the backside of the silicon substrate (10). Etching is terminated substantially automatically by the presence of the silicon oxide strips (12). The thin, single crystal silicon membranes thus formed are suitable for use as diaphragms and microbridges in a microaccelerometers or a pressure sensor.

Patent
28 Jun 1991
TL;DR: In this article, a silicon nitride film is formed between a silicon oxide film and a silica film by chemical vapor deposition process using silica and oxygen as a reaction gas.
Abstract: PURPOSE:To make the precise judgement of terminal for etching back process so as to form a flat insulating film in proper thickness by a method wherein, in order to form the insulating film on a semiconductor substrate, a silicon nitride film is formed between a silicon oxide film and a silica film. CONSTITUTION:An Si substrate 101 is coated with the first silicon oxide film 102. A wirings 103 in specific pattern are formed on the film 102, and then the whole surface is coated with the second oxide film 104 by chemical vapor deposition process using silica and oxygen as a reaction gas. However, the surface of the film 104 is made rugged by the existence of the lower side wirings 3. Accordingly, a silicon nitride film 105 is vapor-deposited on the film 104 using silane and ammonia as another reaction gas; next, while rotating the substrate 101, a solution mainly comprising silanol and alcohol is dripped on the whole surface and then the whole body is heat-treated at 800 deg.C for 30 minutes in nitrogen atmosphere to volatilize any organic constituent as well as to polymerize silanol so that a silica film 106 may be formed thick in the concave part of the film 105 and thin in the convex part of the same. Later, while monitoring the change in the emission spectrum of nitrogen, the films 106, 105 are etched away.

Journal ArticleDOI
TL;DR: In this article, the authors used electron spectroscopy for chemical analysis (ESCA) along the depth from the film surface by Ar-ion etching to determine the gradual changes of the refractive index in the SiOX/SiNXOY interfacial (or transition) region.
Abstract: Si-oxide/Si-oxynitride (SiOX/SiNXOY) double-layer films were prepared by controlling the operation parameters of plasma chemical vapor deposition in N2-diluted silane mixed with H2-diluted silane or with O2 under various mixing ratios. The compositions of the layers of the films were measured with electron spectroscopy for chemical analysis (ESCA) along the depth from the film surface by Ar-ion etching. The results have revealed that O-atoms diffuse into and N-atoms diffuse out of the SiNXOY layer during SiOX layer deposition. By making use of the relation between the refractive index and atomic ratio Si/O or O/N for SiNXOY films, the gradual changes of the refractive index in the SiOX/SiNXOY interfacial (or transition) region has been determined. As a result, the SiOX/SiNXOY double-layer antireflective coating (ARC) has increased the short circuit current density of single-crystal Si solar cells by about 56% in comparison to bare cells.

Proceedings ArticleDOI
24 Jun 1991
TL;DR: In this article, a thermally excited silicon oxide beam resonator based on CMOS technology with subsequent micromachining was designed, manufactured, and characterized, and the acoustic transmission efficiency of the device in air was investigated.
Abstract: The authors designed, manufactured, and characterized a thermally excited silicon oxide beam resonator based on CMOS technology with subsequent micromachining. Besides optical measurements of the resonance frequencies and vibration amplitudes, the acoustic transmission efficiency of the device in air was investigated. At a fundamental resonance of 10.35 kHz, a vibration amplitude of 2 mu m at the tip of the beam with a dynamic heating power P/sub dyn1/=2.5 mW and a sound pressure of 2.8 mPa with P/sub dyn1/=7.4 mW at 4 mm distance from the chip were measured. The oxide beam was simulated with the finite-element program ANSYS to obtain the shape of the resonant modes. >

Patent
02 Oct 1991
TL;DR: In this paper, an infrared absorbing film comprising a synthetic resin and silicon oxide is described, where the silicon oxide was used in an amount of about 2 to about 25% by weight based on the synthetic resin.
Abstract: INFRARED ABSORBING FILM IMPROVED IN TRANSPARENCY Abstract of the disclosure: Disclosed is an infrared absorbing film comprising a synthetic resin and silicon oxide, wherein the silicon oxide is used in an amount of about 2 to about 25% by weight based on the synthetic resin, and wherein the silicon oxide is produced by underwater grinding, has an average particle size of not more than 4 µm, is substantially free of particles exceeding 20 µm in average particle size, and has a specific surface area of not more than 20 m2/g. The film may further comprise a transparent resin layer formed over at least one surface thereof.

Patent
30 May 1991
TL;DR: In this paper, the authors proposed a method to prevent the generation of cracks caused by the difference of thermal expansion coefficients between silicon and semiconductor crystal by growing a silicon oxide film formed on a main plane of a silicon substrate on one side as an insulation mask and constituting an LED array.
Abstract: PURPOSE:To prevent the generation of cracks caused by the difference of thermal expansion coefficients between silicon and semiconductor crystal by growing a silicon oxide film formed on a main plane of a silicon substrate on one side as an insulation mask and constituting an LED array CONSTITUTION:A silicon oxide film 2a is formed on a main face 1a of a silicon substrate 1 on one side The main face 1a is a (100) face The silicon oxide film 2a is partially removed square One side of the square-removed portion 7 of the film is slanted against the crystal direction of The silicon oxide film 2a formed on one side of the main face 1a in this fashion is used as an insulation mask Semiconductor crystal is arranged to make epitaxial growth on a part of the silicon substrate selected by the insulation mask At the same time, the semiconductor crystal 3 is grown from the epitaxial layer in a lateral direction so as to constitute an LED 5, using the growth layer This construction makes it possible to prevent the generation of cracks on the semiconductor crystal layer 3

Journal ArticleDOI
TL;DR: In situ x-ray photoelectron spectroscopy (XPS) allowed as mentioned in this paper to evaluate the effectiveness of this process by studying the Si 2p and O 1s photoemission spectra.
Abstract: Electron cyclotron resonance argon plasmas have been used to clean native silicon oxide at low (≊100 eV) ion energies. In situ x‐ray photoelectron spectroscopy (XPS) allowed us to evaluate the effectiveness of this process by studying the Si 2p and O 1s photoemission spectra. Results indicate complete and rapid removal of chemically bound oxygen to silicon and the presence of small levels of adsorbed or interstitially implanted oxygen. Implanted argon was detected by XPS; however, the concentration appears to be greatly reduced by operating under low substrate bias conditions.

Patent
27 Feb 1991
TL;DR: In this article, a novel green tape composition useful in the manufacture of silver conductor based, low temperature, co-fired multilayer circuit boards comprises from about 8-35% by weight of a calcium-zinc-aluminum-borosilicate devitrifying glass.
Abstract: A novel ceramic green tape composition useful in the manufacture of silver conductor based, low temperature, co-fired multilayer circuit boards comprises from about 8-35% by weight of a calcium-zinc-aluminum-borosilicate devitrifying glass; from about 10-35% by weight of a low alkali borosilicate glass; from about 10-35% by weight of a lead-zinc-aluminosilicate glass; from about 10-35% by weight of a ceramic filler; up to 0.5% by weight of a coloring agent and from about 20-45% by weight of an organic binder. The co-fired multilayer circuit boards made from these green tape compositions have excellent mechanical and electrical properties and have thermal expansion characteristics matching that of silicon. The devitrifying glass comprises from about 10-30% by weight of zinc oxide; from about 10-20% by weight of calcium oxide; up to about 15% by weight of boron oxide; from about 15-20% by weight of aluminum oxide and about 25-55% by weight of silicon oxide. The lead-zinc-aluminosilicate vitreous glass comprises from about 30-40% by weight of lead oxide, from about 6-12% by weight of zinc oxide, from about 6-10% by weight of aluminum oxide and from about 40-55% by weight of silicon oxide. Conductor inks can also be made from the above glasses, and mixtures thereof together with a suitable organic vehicle and a conductive metal such as silver.

Patent
13 Aug 1991
TL;DR: In this paper, an insulating adhesive is used to fix and bond a semiconductor substrate to a lead frame, and the substrate's surface is provided with an oxide film other than a silicon oxide.
Abstract: PURPOSE:To sharply enhance the hardness at a high temperature after hardening, to enhance a wire bonding property and to obtain a device whose reliability is high by a method wherein an insulating adhesive which fixes and bonds an insulating substrate onto a bed contains a metal whose surface is provided with an oxide film other than a silicon oxide. CONSTITUTION:In a device where a semiconductor pellet and an insulating substrate 2 have been mounted respectively on a bed 1a of a lead frame 1, the insulating substrate 2 is fixed and bonded onto the bed 1a by using an insulating adhesive 3, and the insulating adhesive 3 contains a metal whose surface is provided with an oxide film other than a silicon oxide. Since the insulating adhesive contains the metal in addition to the silicon oxide in this case, the content by percentage of a filler becomes high and the hardness after hardening is enhanced. When a filling rate is increased, a wire bonding operation can be executed at an optimum temperature. In this manner, sufficient hardness is obtained even at a high temperature after hardening, and an excellent wire bonding property and high reliability are provided.

Patent
25 Jun 1991
TL;DR: In this article, a first layer of borophosphosilicate glass is deposited on the integrated circuit array, followed immediately by a thin cap layer of undoped oxide of silicon.
Abstract: A method for encapsulation of an integrated circuit array that suppresses or eliminates absorption and subsequent out-gassing of water vapor and suppresses or eliminates out-gassing of toxic constituents of the encapsulation layer such as trimethyl borate. A first layer of borophosphosilicate glass is deposited on the integrated circuit array, followed immediately by deposit of a thin cap layer of undoped oxide of silicon. The method also allows use of boron and phosphorous concentrations in the borophosphosilicate glass as high as 9 weight percent with no loss of stability of that layer, before or after thermal treatment. Reflow processing temperatures as low as T r =700°-900° C. may be used here. Alternatively, silicon nitride can replace the silicon oxide in the cap layer, using either a high temperature process or a lower temperature plasma-enhanced process.

Patent
02 Aug 1991
TL;DR: In this paper, a flexible polymer substrate, particularly useful for medical or food packaging applications, defines a surface that carries a thin film with a thickness less than about 1000 A and preferably the surface and thin film together have a permeability to oxygen gas that is less than 0.1 cc/100in²/day.
Abstract: A flexible polymer substrate, particularly useful for medical or food packaging applications, defines a surface that carries a thin film. The thin film has a thickness less than about 1000 A and preferably the surface and thin film together have a permeability to oxygen gas that is less than about 0.1 cc/100in²/day. The thin film includes a substantially inorganic silicon oxide. The film is deposited in a previously evacuated chamber by glow discharge from a gas stream that includes a volatilized organosilicon component, an oxygen component, and an inert gas component.

Patent
26 Nov 1991
TL;DR: In this paper, the authors proposed a method for depositing a passivation layer on a semiconductor structure having a high resistance value polysilicon layer formed thereon while maintaining the high resist value thereof.
Abstract: A method for depositing a passivation layer on a semiconductor structure having a high resistance value polysilicon layer formed thereon while maintaining the high resistance value thereof and comprises sequentially depositing a silicon oxide layer and a silicon nitride layer, on a high resistance value polysilicon layer of a partially completed semiconductor structure to form a passivation layer thereover. The passivation layer including the silicon oxide layer and the silicon nitride layer is annealed with oxygen plasma in a chamber. The annealed passivation layer is then heated in the presence of a conditioning gas in the chamber to thereby maintaining the resistance of the high resistance value polysilicon layer.

Patent
26 Apr 1991
TL;DR: In this article, the authors proposed to reduce expansion of a volume due to oxidation and to eliminate a step and concentration of stress on a semiconductor substrate by making an oxidation region porous selectively before oxidizing the substrate selectively.
Abstract: PURPOSE:To reduce expansion of a volume due to oxidation and to eliminate a step and concentration of stress on a semiconductor substrate by making an oxidation region porous selectively before oxidizing a semiconductor substrate selectively. CONSTITUTION:After a pad silicon oxide film 2 is formed all over a semiconductor substrate 1, a silicon nitride film 3 is formed all over there. Then, the silicon nitride film 3 excepting a region which becomes a transistor and the oxide film 2 are selectively etched and removed using a resist as a mask to expose the substrate 1. A current, is made to flow in hydrofluoric acid solution wherein ethanol is mixed and stored using a P-type silicon substrate 1 as an anode. Numberless fine holes are formed in a region which becomes a transistor of the substrate 1 which is exposed using the silicon nitride film 3 as a mask to provide a porous silicon region 4. A thick isolation oxide film 5 is formed by selectively oxidizing the porous silicon region 4 using the silicon nitride film 3 as a mask. Thereby, it is possible to restrain expansion of the volume in the region of the isolation oxide film 5 and to restrain a step and concentration of stress on the substrate 1.

Journal ArticleDOI
TL;DR: In this paper, positive and negative charging effects are described for small area (0.008-20 μm2), very thin dielectric (∼2.5 nm), metaloxide-silicon diodes in which electrons can tunnel directly between the electrodes.
Abstract: Positive and negative charging effects are described for small area (0.008–20 μm2), very thin dielectric (∼2.5 nm), metal‐oxide‐silicon diodes in which electrons can tunnel directly between the electrodes. These effects are similar to those seen in conventional, thicker oxide devices in which electrons are injected into the oxide conduction band. We show that at least in the thin oxides, charge generation is possible at a total electron energy level which is well below those suggested in a number of models for damage in the thicker oxides.

Patent
Yamazaki Toru1
21 Oct 1991
TL;DR: In this article, the U-trench isolation region is constituted with a U-Trench provided such that it penetrates the field oxide film, a channel stopper provided in a portion of the silicon substrate exposed on a bottom face of the Utrench, and a fourth film in a form of an insulating film connected to the top face of a third film at an upper end of said U-torench and covering the UtoTrench.
Abstract: In a semiconductor device having an element isolation region including a LOCOS type field oxide film formed in a surface of a silicon substrate and a U-trench isolation region provided in the silicon substrate, the U-trench isolation region is constituted with a U-trench provided such that it penetrates the field oxide film, a channel stopper provided in a portion of the silicon substrate exposed on a bottom face of the U-trench, a first film in a form of a silicon oxide film formed by thermal oxidation of an exposed portion of the silicon substrate in the U-trench, a second film comprising a buried layer having thermal reflow characteristics and burying the U-trench, a third film having non-thermal reflow characteristics and having a top face substantially coplanar with a top face of the field oxide film and a bottom face connected to a top face of the second films and a fourth film in a form of an insulating film connected to the top face of the third film at an upper end of said U-trench and covering the U-trench. In the element isolation region having this structure, there is no leakage current produced due to thermal oxidation of a polysilicon film buried in the U-trench, contrary to the conventional U-trench isolation region having buried polysilicon film. Further, increase of parasitic capacitance which is caused by thermal oxidation of the buried polysilicon layer can be also restricted.

Patent
20 Dec 1991
TL;DR: In this paper, a DRAM having stacked high capacitance capacitors is formed by depositing a thick undoped polysilicon layer over field oxide areas thereon, patterning the poly silicon layer so as to have portions over the planned stacked capacitor areas.
Abstract: A DRAM having stacked high capacitance capacitors formed by depositing a thick undoped polysilicon layer over field oxide areas thereon, patterning the polysilicon layer so as to have portions over the planned stacked capacitor areas, forming a silicon oxide layer on the exposed surface of the polysilicon, removing the silicon oxide layer from horizontal surfaces of the polysilicon layer by anisotropic etching, removing the polysilicon layer by isotropic etching leaving vertical silicon oxide structures, and forming openings to desired source/drain structures of the DRAM using lithography and etching. A bottom electrode polysilicon layer is deposited over the device and field oxide areas to make contact to the source/drain structures. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top storage node electrode and the contact polysilicon layer and the dielectric layers are patterned.