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Showing papers on "Silicon oxide published in 1998"


Journal ArticleDOI
14 Aug 1998-Science
TL;DR: The experimentally determined structure resembles a coaxial nanocable with a semiconductor-insulator-metal (or semiconductors-metal-semiconductor) geometry and suggests applications in nanoscale electronic devices that take advantage of this self-organization mechanism for multielement nanotube formation.
Abstract: Multielement nanotubes comprising multiple phases, with diameters of a few tens of nanometers and lengths up to 50 micrometers, were successfully synthesized by means of reactive laser ablation. The experimentally determined structure consists of a β-phase silicon carbide core, an amorphous silicon oxide intermediate layer, and graphitic outer shells made of boron nitride and carbon layers separated in the radial direction. The structure resembles a coaxial nanocable with a semiconductor-insulator-metal (or semiconductor-insulator-semiconductor) geometry and suggests applications in nanoscale electronic devices that take advantage of this self-organization mechanism for multielement nanotube formation.

492 citations


Journal ArticleDOI
TL;DR: In this article, a large-scale synthesis of silicon nanowires (SiNWs) using a simple but effective approach was reported, where high purity SiNWs of uniform diameters around 15 nm were obtained by sublimating a hot-pressed silicon powder target at 1200 °C in a flowing carrier gas environment.
Abstract: We report the large-scale synthesis of silicon nanowires (SiNWs) using a simple but effective approach. High purity SiNWs of uniform diameters around 15 nm were obtained by sublimating a hot-pressed silicon powder target at 1200 °C in a flowing carrier gas environment. The SiNWs emit stable blue light which seems unrelated to quantum confinement, but related to an amorphous overcoating layer of silicon oxide. Our approach can be used, in principle, as a general method for synthesis of other one-dimensional semiconducting, or conducting nanowires.

362 citations


Journal ArticleDOI
TL;DR: In this article, the surface charge accumulation on the electrode passivation of silicon cantilever actuators has been observed, and charge decay characteristics were recorded for a silicon oxide passivation and a multilayer passivation by silicon oxide and silicon nitride.
Abstract: Silicon dioxide and silicon nitride coatings are preferably used as dielectric layers for short-circuit protection in capacitive silicon microsensors and microactuators. However, their tendency to electrostatic charging can diminish the device reliability. Gas discharges in the air gap of silicon cantilever actuators have been observed, resulting in surface charge accumulation on the electrode passivation of the devices. Charge decay characteristics were recorded for a silicon oxide passivation and a multilayer passivation by silicon oxide and silicon nitride. The charges are found to be highly stable in time. Based on these observations, rules for the application and design of dielectric layers in microdevices are proposed.

315 citations


Journal ArticleDOI
TL;DR: In this paper, a growth mechanism was proposed based on the microstructure and different morphologies of the Si nanowires observed by means of transmission electron microscopy (TEM).
Abstract: Nucleation and growth of Si nanowires by laser ablation and thermal evaporation of Si powder sources mixed with ${\mathrm{SiO}}_{2}$ have been investigated by means of transmission electron microscopy. At the initial nucleation stage, Si oxide vapor condensed on the substrate and formed Si nanoparticles (the nuclei of nanowires). Each Si nanowire nucleus consisted of a polycrystalline Si core containing a high density of defects and a Si oxide shell. A growth mechanism was proposed based on the microstructure and different morphologies of the Si nanowires observed.

292 citations


Journal ArticleDOI
TL;DR: In this article, a review of extensive studies involving the in situ sol-gel reactions of the alkoxides of silicon, titanium, aluminum, zirconium and organoalkoxysilanes, as well as their mixtures and two step reactions involving these monomers are presented.

210 citations


Patent
13 Jan 1998
TL;DR: In this paper, a gas-sensing semiconductor device is fabricated on a silicon substrate, having a thin silicon oxide insulating layer (3) on one side and a very thin silicon layer (4) on top of the IC using CMOS SOI technology.
Abstract: A gas-sensing semiconductor device (1) is fabricated on a silicon substrate (2) having a thin silicon oxide insulating layer (3) on one side and a thin silicon layer (4) on top of the insulating layer (3) using CMOS SOI technology. The silicon layer (4) may be in the form of an island surrounded by a silicon oxide insulating barrier layer (4) formed by the known LOCOS oxidation technique, although other lateral isolation techniques may also be used. The device (1) includes at least one sensing area provided with a gas-sensitive layer (18), a MOSFET heater (6) for heating the gas-sensitive layer (18) to promote gas reaction with the gas-sensitive layer (18) and a sensor (16), which may be in the form of a chemoresistor, for providing an electrical output indicative of gas reaction with the gas-sensitive layer (18). As one of the final fabrication steps, the substrate (2) is back-etched so as to form a thin membrane (20) in the sensing area. Such a device can be produced at low cost using conventional CMOS SOI technology.

191 citations


Patent
22 Sep 1998
TL;DR: In this article, the authors proposed a method of film formation in which a silicon oxide film (a NSG film: a Non-doped Silicate Glass) is formed on a substrate having a recess by a CVD method using a mixed gas containing TEOS and ozone.
Abstract: This invention relates to a method of film formation in which, when a silicon oxide film (a NSG film: a Non-doped Silicate Glass) is formed on a substrate having a recess by a CVD method using a mixed gas containing TEOS and ozone, surface dependency on the substrate is eliminated to embed a silicon oxide film into the recess of the surface. The invention includes forming a phosphorus containing insulating film as a base layer on the surface of a substrate and forming a silicon-containing insulating film on the phosphosilicate glass film by the chemical vapor deposition method, using a mixture of a ozone-containing gas and a silicon-containing gas.

167 citations


Journal ArticleDOI
Xin Guo1, Tso-Ping Ma1
TL;DR: In this paper, the authors examined the gate leakage current as a function of the oxygen and nitrogen contents in ultrathin silicon oxynitride films on Si substrates and showed that, provided that electron tunneling is the dominant current conduction mechanism, the leakage current in the direct tunneling regime increases monotonically with the oxygen content for a given equivalent oxide thickness, such that pure silicon nitride passes the least amount of current while pure silicon oxide is the leakiest.
Abstract: It is widely known that the addition of nitrogen in silicon oxide, or the addition of oxygen in silicon nitride, affects its reliability as a gate dielectric. The authors examine the gate leakage current as a function of the oxygen and nitrogen contents in ultrathin silicon oxynitride films on Si substrates. It is shown that, provided that electron tunneling is the dominant current conduction mechanism, the gate leakage current in the direct tunneling regime increases monotonically with the oxygen content for a given equivalent oxide thickness (EOT), such that pure silicon nitride passes the least amount of current while pure silicon oxide is the leakiest.

164 citations


Patent
Makoto Nagamine1, Hitoshi Itoh1
17 Mar 1998
TL;DR: In this paper, a method of manufacturing a semiconductor device, which comprises the steps of forming an oxide film by oxidizing a surface of semiconductor in an atmosphere containing an oxygen-activated species, and removing the oxide film so as to expose the surface of the semiconductor.
Abstract: A method of manufacturing a semiconductor device, which comprises a step of forming an oxide film by oxidizing a surface of semiconductor layer in an atmosphere containing an oxygen-activated species at a temperature of over 550° C. A method of manufacturing a semiconductor device, which comprises the steps of forming an oxide film by oxidizing a surface of semiconductor in an atmosphere containing an oxygen-activated species, and removing the oxide film so as to expose a surface of the semiconductor. A method of manufacturing a semiconductor device which comprises a step of feeding an oxidizing source gas comprising as a main component oxygen atomic radicals of singlet state in an excited state to a silicon layer thereby to oxidize a surface of the silicon layer, thus forming a silicon oxide film.

157 citations


Patent
Tadashi Oshima1
25 Feb 1998
TL;DR: In this paper, a silicon nitride layer on a silicon layer or a silicon oxide layer is formed by loading the silicon or the silicon oxide layers and the silicon n-oxide layer in a dry etching atmosphere, and selectively etching the silicon polysilicon oxide layer with respect to the silicon and silicon oxide by flowing a fluorine gas consisting of any one of CH 2 F 2, CH 3 F, or CHF 3 and an inert gas.
Abstract: There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH 2 F 2 , CH 3 F, or CHF 3 and an inert gas to the dry etching atmosphere Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO 2 can be enhanced and also etching anisotropy can be enhanced

133 citations


Patent
13 Aug 1998
TL;DR: In this paper, a process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate via use of a thin silicon oxide layer, has been developed.
Abstract: A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is created in the semiconductor substrate, in a region between insulator spacers, on a gate structure, and insulator filled, shallow trench regions, resulting in lightly doped source/drain segments, remaining under the masking insulator spacers. After a thin silicon oxide layer is formed on the exposed silicon surfaces, in the openings, a silicon deposition, and etch back procedures are performed, partially refilling the openings to a depth that still allows the thin silicon oxide layer to be exposed on the sides of the lightly doped source/drain segment. After removal of the exposed portion of the thin silicon oxide layer, and after deposition and etch back of another silicon layer, completely filling the openings, a heavily doped source/drain region is formed in the silicon layers, residing in the openings.

Journal ArticleDOI
TL;DR: In this paper, a mixture of SiC and Co powders, deposited on silica substrates and heated under an Ar/CO atmosphere at ca. 1500C, produced material with unusual three-dimensional (3D) networks of nanofibers of uniform diameter (ca. 20-120nm) and length (ca 10-250mu;m).
Abstract: Novel flower-like nanostructures consisting of silicon oxide nanofibers, radially attached to a single catalytic particle, were generated by solid-solid and gas-solid reactions under a temperature gradient. In this process, a mixture of SiC and Co powders, deposited on silica substrates and heated under an Ar/CO atmosphere at ca. 1500C, produced material with unusual three-dimensional (3D) networks of nanofibers of uniform diameter (ca. 20-120nm) and length (ca. 10-250mu;m). Scanning electron microscopy (SEM), high resolution transmission electron microscopy (HRTEM), X-ray powder diffraction and energy dispersive X-ray (EDX) analyses reveal that the nanofibres are amorphous and consist only of silicon oxide, generated from the reaction of CO with SiC. Nanostructure formation is catalyzed by Co particles, which act as nucleation sites and templates for 3D growth. Experiments using Si3N4 and Si in conjunction with other catalysts (e.g. Fe, Ni and CoO) yield similar results and confirm that the resulting SiOx fibres display virtually unique and remarkable radial growth starting from single metal particles. These structures exhibit morphologies comparable to radiolarian and diatom skeletons and may provide insight into the formation of microbiological systems.

Patent
19 Mar 1998
TL;DR: In this article, an integral magnetic head suspension is fabricated on silicon wafers using semiconductor processes, with or without the head, containing integrated conductive circuits that have multiple cross overs for noise reduction.
Abstract: The present invention is an integral magnetic head suspension and method for making the same. The integral suspension, with or without the head, contains integrated conductive circuits that have multiple cross overs for noise reduction. The suspension is fabricated completely on silicon (Si) wafers using semiconductor processes. A N+ silicon layer is disposed over a P- silicon wafer. The N+ silicon layer and the P- silicon water are thermally oxidized to generate a bottom silicon oxide layer opposite the N+ layer side of the wafer and a top silicon oxide layer on the N+ side of the wafer, and to drive the N+ silicon into the P- silicon wafer. A layer of polysilicon is disposed over the silicon oxide layer on top of the N+ silicon layer. One or more pairs of conductive traces having multiple cross-overs are fabricated on the layer of polysilicon. Optimally, a magnetic head is simultaneously fabricated on the suspension. The polysilicon layer is then patterned to define the head structure and suspension structure as one piece. Finally, the magnetic head and suspension are separated from the wafer by removing the first silicon oxide layer by a chemical etchant and the P- silicon wafer by selective etching. The head and suspension are released from the silicon wafer as a single structure using the above-described semiconductor processes. Accordingly, no grinding or cutting is used to define the dimensions of the head. Further, no processes are required to attach the head to the suspension and the suspension can be made from low mass materials such as silicon (Si) or Al 2 O 3 .

Journal ArticleDOI
TL;DR: In this article, polycarbosilane-derived SiC fibers, Nicalon, Hi-Nicalon and S, were exposed for 1 to 100 h at 1273-1773 K in air.

Journal ArticleDOI
TL;DR: In this article, a magnetron-sputtered silicon oxide films after they were annealed at about 1000°C in the N2 atmosphere were observed to have an intense ultraviolet photoluminescence centered at 370 nm, which was associated with the formation of nanocrystal silicon particles in the specially structured SiO2, which highly resembles the oxide layer of porous silicon.
Abstract: Intense ultraviolet photoluminescence centered at 370 nm was observed from magnetron-sputtered silicon oxide films after they were annealed at about 1000 °C in N2 atmosphere. This photoluminescence is found to be associated with the formation of nanocrystal silicon particles in the specially structured SiO2, which highly resembles the oxide layer of porous silicon. The luminescence centers at the interface between the nanocrystal silicon particles and the SiO2 matrix are responsible for the strong ultraviolet luminescence.

Patent
23 Oct 1998
TL;DR: In this article, a method of forming a crystalline silicon well over a silicon oxide barrier layer, preferably for use in formation of a tunneling diode, is presented, where a silicon substrate is provided of predetermined crystallographic orientation.
Abstract: A method of forming a crystalline silicon well over a silicon oxide barrier layer, preferably for use in formation of a tunneling diode. A silicon substrate is provided of predetermined crystallographic orientation. A layer of crystallographic silicon oxide is formed over the silicon substrate and substantially matched to the crystallographic orientation of the silicon substrate. A layer of crystallographic silicon is formed over the silicon oxide layer substantially matched to the crystallographic orientation of the silicon oxide layer. The layer of silicon oxide is formed by the steps of placing the silicon substrate in a chamber having an oxygen ambient and heating the substrate to a temperature in the range of from about 650 to about 750 degrees C. at a pressure of from about 10−4 to about 10−7 until the silicon oxide layer has reached a predetermined thickness. In the case of a tunneling diode, the layer of silicon oxide has a thickness of from about 2 to about 8 monolayers and the layer of crystallographic silicon has a thickness of from about 2 to about 8 monolayers. A second layer of silicon oxide is provided on the layer of silicon remote from the layer of crystallographic silicon oxide. In the case of a silicon-on-insulator-type structure, the layer of crystallographic silicon oxide is from about 500 to about 2000 Angstroms and preferably 1000 Angstroms and the layer of silicon is from about 50 to about 1000 Angstroms and preferably 100 Angstroms.

Journal ArticleDOI
01 Jan 1998-Polymer
TL;DR: In this paper, NAFION®/silicon oxide hybrid was prepared from solution by hydrolysis/polycondensation of alkoxy silanes and showed a lamellar structure by transmission electron microscopy.

Journal ArticleDOI
TL;DR: In this paper, the effect of ultraprecision grinding on microstructural change in silicon monocrystals, such as surface roughness and dislocation structure, was investigated both experimentally and theoretically.

Patent
Hiraku Ishikawa1
08 Jun 1998
TL;DR: In this article, an isolation trench is formed on a substrate to isolate a plurality of semiconductor elements, and then a thermal oxide film is created on a sidewall of the trench, whereupon a silicon oxide film was formed on the substrate by chemical vapor deposition.
Abstract: In fabrication of a semiconductor device, firstly an isolation trench is formed on a substrate to isolate a plurality of semiconductor elements, and then a thermal oxide film is formed on a sidewall of the trench, whereupon a silicon oxide film is formed on the substrate by chemical vapor deposition. Finally the entire substrate is annealed in a high-pressure ambient.

Patent
16 Nov 1998
TL;DR: In this paper, a process for curing low-k spin-on dielectric layers based on alkyl silsesquioxane polymers by laser scanning is described wherein curing is achieved by both photothermal and photochemical mechanisms.
Abstract: A process for curing low-k spin-on dielectric layers based on alkyl silsesquioxane polymers by laser scanning is described wherein curing is achieved by both photothermal and photochemical mechanisms. The layers are deposited by spin deposition, dried and cured by raster scanning with a pulsed laser at energies between 0.1 and 1 Joules/cm 2 . Because the laser causes heating of the layer, a nitrogen jet is applied in the wake of the scanning laser beam to rapidly cool the layer and to inhibit oxidation and moisture absorption. The laser induced heating also assists in the discharge of moisture and by-products of the polymerization process. The laser operates at wavelengths between 200 and 400 nm. Insulative layers such as silicon oxide are sufficiently transparent at these so that oxide segments overlying the polymer layer do not inhibit the curing process. Implementation of the laser scanning feature is readily incorporated into an existing spin-on deposition and curing tool.

Journal ArticleDOI
TL;DR: In this paper, a silicon oxide layer was prepared using a mixture of an organosilicon compound, that is, tetramethylsilane or tetramethoxysilane, and oxygen as a source gas.

Patent
15 Jul 1998
TL;DR: In this article, a method for forming self-aligned, metal silicide (salicide), layers, on polysilicon gate structures, and on source/drain regions, located in a first region of a semiconductor substrate, while avoiding the salicide formation, was developed.
Abstract: A method for forming self-aligned, metal silicide, (salicide), layers, on polysilicon gate structures, and on source/drain regions, located in a first region of a semiconductor substrate, while avoiding the salicide formation, on polysilicon gate structures, and on source/drain regions, located in a second region of a semiconductor substrate, has been developed. A composite insulator shape, comprising an overlying silicon nitride layer, and an underlying TEOS deposited, silicon oxide layer, is used to block polysilicon, as well as silicon regions, in the second region of the semiconductor substrate, from salicide formation. Unwanted silicon oxide spacers, created on the sides of polysilicon gate structures, during the patterning of the composite insulator shape, is selectively removed using dilute hydrofluoric acid solutions.

Journal ArticleDOI
TL;DR: In this article, the interphase region between the deposited layer and the poly(ethylene terephthalate) (PET) substrate has been investigated and compared to physical vapor deposited (PVD) (electron beam evaporated) SiO2.
Abstract: The “interphase” region between the deposited layer [e.g., plasma-enhanced chemically vapor deposited (PECVD) SiO2 or SiN] and the poly(ethylene terephthalate) (PET) substrate has been investigated and compared to physical vapor deposited (PVD) (electron beam evaporated) SiO2. Composition profiles determined by time-of-flight elastic recoil detection, electron microprobe analysis, and x-ray photoelectron spectroscopy all show an extended interphase region more than 50 nm in width, while the profile of the PVD SiO2 is narrower. However, since these analytical techniques are invasive and prone to artifacts, we have also examined ultrathin (about 10 and 20 nm) SiO2 and SiN PECVD layers on 50 nm spin-coated PET substrates by nondestructive infrared (IR) techniques. The IR spectra confirm that the thin PECVD deposits also comprise an organosilicon phase with Si–CHx bonds. We explain these observations in terms of a fragmentation/redeposition mechanism: During the earliest stage of PECVD, interaction between th...

Patent
10 Apr 1998
TL;DR: In this paper, the authors propose a method for easily manufacturing an element structure which has a plurality of vertical MOS transistors, arranged in a vertical direction to a substrate surface and connected in series.
Abstract: PROBLEM TO BE SOLVED: To provide a method for easily manufacturing an element structure which has a plurality of vertical MOS transistors, arranged in a vertical direction to a substrate surface and connected in series. SOLUTION: A silicon oxide film 42, a polysilicon film, 43, a silicon oxide film 44, a polysilicon film 45, a silicon oxide film 46 and a polysilicon film 47 are formed sequentially on a substrate 40 having an n type source/drain diffusion layer 41 formed therein. The laminated films 43 to 47 are then subjected to an inland-shape patterning process. The film laminates 43 to 47 are next formed therein with an opening 50. Next, a gate insulating film 51 is formed on a side wall of the opening 50, and then the opening 50 is buried with a polysilcon film 52. An n-type source/drain diffusion layer 53 is formed above the polysilicon film 52.

Journal ArticleDOI
TL;DR: The photoluminescence properties of H-rich amorphous silicon oxide thin films grown in a dual-plasma chemical vapor deposition reactor have been related to a number of stoichiometry and structure characterizations.
Abstract: In order to understand the radiative recombination mechanisms in silicon oxides, photoluminescence properties (PL) of H-rich amorphous silicon oxide thin films grown in a dual-plasma chemical vapor deposition reactor have been related to a number of stoichiometry and structure characterizations (x-ray photoelectron spectroscopy, vibrational spectroscopy, and gas evolution studies). The visible photoluminescence at room temperature from a-SiOx:H matrixes with different compositions, including different bonding environments for H atoms, has been studied in the as-deposited and annealed states up to 900 °C. Three commonly reported PL bands centered around 1.7, 2.1, and 2.9 eV have been detected from the same type of a-SiOx:H material, only by varying the oxygen content (x = 1.35, 1.65, and 2). Temperature quenching experiments are crucial to distinguish the 1.7 eV band, fully consistent with bandtail-to-bandtail recombination, from the radiative defect luminescence mechanisms attributed either to defects rel...

Journal ArticleDOI
TL;DR: Oxygen-implanted silicon-on-insulator (SIMOX) material, or SIMOX (separation by implantation of oxygen), is another chapter in the continuing development of new material technologies for use by the semiconductor industry as discussed by the authors.
Abstract: Oxygen-implanted silicon-on-insulator (SOI) material, or SIMOX (separation by implantation of oxygen), is another chapter in the continuing development of new material technologies for use by the semiconductor industry. Building integrated circuits (ICs) in a thin layer of crystalline silicon on a layer of silicon oxide on a silicon substrate has benefits for radiationhard, high-temperature, high-speed, low-voltage, and low-power operation, and for future device designs. Historically the first interest in SIMOX was for radiation-hard electronics for space, but the major application of interest currently is low-power, high-speed, portable electronics. Silicon-on-insulator also avoids the disadvantage of a completely different substrate such as sapphire or gallium arsenide. Formation of a buried-oxide (BOX) layer by high-energy, high-dose, oxygen ion implantation has the advantage that the ion-implant dose can be made extremely precise and extremely uniform. However the silicon and oxide layers are highly damaged after the implant, so high-temperature annealing sequences are required to restore devicequality material. In fact SIMOX process development necessitated the development of new technologies for high-dose implantation and high-temperature annealing.

Journal ArticleDOI
01 Sep 1998-Wear
TL;DR: In this paper, the performance of various abrasives for CMP of uniaxially pressed Si3N3 bearing balls by magnetic float polishing (MFP) was investigated.

Patent
27 Jul 1998
TL;DR: A collection of nanoscale particles are a composite of carbon and metal oxide or silicon oxide, and can be produced by laser pyrolysis as discussed by the authors, which involves the formation of a molecular stream including a metal precursor, an infrared absorber, an oxidizing agent and a carbon precursor.
Abstract: A collection of nanoscale particles are a composite of carbon and metal oxide or silicon oxide. The composite particles have an average diameter from about 5 nm to about 1000 nm, and can be produced by laser pyrolysis. The laser pyrolysis involves the formation of a molecular stream including a metal precursor, an infrared absorber, an oxidizing agent and a carbon precursor. The pyrolysis is driven by heat absorbed from a laser beam. Furthermore, nanoparticles including titanium oxide with a rutile crystal structure have been produced.

Patent
22 May 1998
TL;DR: In this paper, a three-layered polysilicon oxide laminate was used to cover the surface of the n-type nitride semiconductor layers with a laminate, comprising a first layer made of an insulating film, a metal layer formed on the first layer, and a second layer made on the metal layer.
Abstract: PROBLEM TO BE SOLVED: To emit light at a high luminance with few short-circuits by providing a protective film covering the surface of nitride semiconductor layers with a laminate, comprising a first layer made of an insulating film, a metal layer formed on the first layer, and a second layer made of an insulating film and formed on the metal layer. SOLUTION: After forming an n-type nitride semiconductor film and a film of a p-type nitride semiconductor on a sapphire substrate 104, the p-type nitride semiconductor is etched in part to thereby expose the surface of the n-type nitride semiconductor layer. After forming electrodes 110, 111 and 112 on the p and n-type nitride semiconductors, a silicon oxide film is formed over the whole surface. Etching is effected, using the silicon oxide film as a mask to thereby expose part of the electrode surfaces, and an insulating film which is a first layer 101 is formed. Then, a platinum film is formed to thereby form a metal layer 102 on the layer 101. Furthermore, a second layer 103 of an insulating layer is formed on the layer 102 by processing the silicon oxide film by a plasma CVD method. As a result, a three-layered protective film is formed.

Journal ArticleDOI
TL;DR: In this article, the true chemical shift of silicon oxide layers thicker than 2 nm was determined to be ∼3.8 ǫ eV, and the dependence of the energy shift on the oxide thickness almost disappears with the deposition of a thin palladium overlayer, because of avoidance of the surface charging effect due to photoemission and because of the nearly constant energy shift resulting from extra atomic relaxation.
Abstract: The energy difference between the oxide and substrate Si 2p peaks for silicon oxide/Si structures increases with the oxide thickness. The dependence of the energy shift on the oxide thickness almost disappears with the deposition of a thin palladium overlayer, because of the avoidance of the surface charging effect due to photoemission and because of the nearly constant energy shift resulting from extra atomic relaxation. The true chemical shift of silicon oxide layers thicker than 2 nm is determined to be ∼3.8 eV. For the thickness dependence of the oxide Si 2p energy, the extra atomic relaxation and charging effect are dominant for oxide layers thinner than ∼2 nm and thicker than ∼4 nm, respectively. In the intermediate thickness region, both the effects are important.