Showing papers on "Silicon oxide published in 1999"

Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound

Abstract: A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40° C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.0.

Method of silicon oxide and silicon glass films deposition

Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using soft power-optimized Plasma-Activated CVD with a TEOS-ozone-oxygen reaction gas mixture (TEOS O3/O2 PACVD) is described. It combines advantages of both low temperature Plasma-Enhanced Chemical Vapor Deposition (PECVD) and TEOS-ozone Sub-Atmospheric Chemical Vapor Deposition (SACVD) and yields a coating of silicon oxide with stable and high deposition rate, no surface sensitivity, good film properties, conformal step coverage and good gap-fill. Key features of the invention's O3/O2 PACVD process are: a plasma is maintain throughout the entire deposition step in a parallel plate type reactor chamber, the precise RF plasma density, ozone concentration in oxygen and the deposition temperature. These features provide the reaction conditions for the proper O3/O2 reaction mechanism that deposits a conformal silicon oxide layer. The process has significant implication for semiconductor device manufacturing involving the deposition of a dielectric over a conducting non-planar surface.

Cvd nanoporous silica low dielectric constant films

Abstract: A method and apparatus for depositing nano-porous low dielectric constant films by reaction of a silicon hydride containing compound or mixture optionally having thermally labile organic groups with a peroxide compound on the surface of a substrate. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a foam structure. The nano-porous silicon oxide based films are useful for filling gaps between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures. Preferred nano-porous silicon oxide based films are produced by reaction of 1,3,5-trisilanacyclohexane, bis(formyloxysilano)methane, or bis(glyoxylylsilano)methane and hydrogen peroxide followed by a cure/anneal that includes a gradual increase in temperature.

Method for etching a trench having rounded top and bottom corners in a silicon substrate

Abstract: The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

Surface treatment of C-doped SiO2 film to enhance film stability during O2 ashing

Abstract: A method for forming an insulation layer over a substrate. The method forms a carbon-doped silicon oxide layer by thermal chemical vapor deposition using an organosilane. The carbon-doped silicon oxide layer is subsequently cured and densified. In one embodiment, the cured film is densified in a nitrogen-containing plasma. The method is particularly suitable for deposition of low dielectric constant films, i.e., where k is less than or equal to 3.0. Low-k, carbon-doped silicon oxide methylsilane or di-, tri-, tetra-, or phenylmethylsilane. and ozone. The above method can be carried out in a substrate processing system having a process chamber; a substrate holder, a heater, a gas delivery system, and a power supply, all of which are coupled to a controller. The controller contains a memory having a computer-readable medium with a program embodied for directing operation of the system in accordance with above method.

Thermal CVD process for depositing a low dielectric constant carbon-doped silicon oxide film

Abstract: A method for providing a dielectric film having a low dielectric constant. The deposited film is particularly useful as an intermetal or premetal dielectric layer in an integrated circuit. The low dielectric constant film is a carbon-doped silicon oxide layer deposited from a thermal, as opposed to plasma, CVD process. The layer is deposited from a process gas of ozone and an organosilane precursor having at least one silicon-carbon (Si—C) bond. During the deposition process the wafer is heated to a temperature less than 250° C. and preferably to a temperature between 100-200° C. Enhancements to the process include adding Boron and/or Phosphorus dopants, two step deposition, and capping the post cured layer.

Enhancement of silicon oxide etch rate and nitride selectivity using hexafluorobutadiene or other heavy perfluorocarbon

Abstract: A plasma etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. A primary fluorine-containing gas, preferably hexafluorobutadiene (C 4 F 6 ), is combined with a significantly larger amount of the diluent gas xenon (Xe) enhance nitride selectivity without the occurrence of etch stop. The chemistry is also useful for etching oxides in which holes and corners have already been formed, for which the use of xenon also reduces faceting of the oxide. For this use, the relative amount of xenon need not be so high. The invention may be used with related heavy fluorocarbons and other fluorine-based etching gases.

Characterization of silicon surface preparation processes for advanced gate dielectrics

Abstract: This paper gives a short overview of issues associated with the surface preparation of silicon surfaces for advanced gate dielectrics and the appearance and nature of the wafer surface after different chemical treatments. The main portion of the paper demonstrates the use of electrochemical open-circuit potential (OCP) measurements as a simple and powerful technique to investigate and characterize wet silicon surface-preparation processes. This technique provides unique information about the evolution of semiconductor surface reactions in wet- chemical environments and permits the investigation of the kinetics of oxidation and etching processes in situ and in real time. Very good agreement between results obtained by this technique and results from multiple internal reflection-Fourier transform infrared spectroscopy (MIR-FTIR), X-ray photoelectron spectroscopy (XPS), spectroscopic ellipsometry (SE), and contact-angle studies is presented in this paper. A model is also presented which permits the correlation of the measured open circuit potential difference to the thickness of a growing native oxide. The etching behavior of an ultrathin thermally grown silicon oxide layer in hydrofluoric acid (HF) is discussed as a new result obtained using the OCP technique.

Method for anisotropic plasma-chemical dry etching of silicon nitride layers using a gas mixture containing fluorine

Abstract: An etching gas mixture containing CHF3, SF6 and a non-oxidizing gas such as Ar is used as an etching gas mixture for the anisotropic plasma-chemical dry-etching of a silicon nitride layer differentially or selectively relative to a silicon oxide layer. The gas mixture does not contain oxygen, chlorine, bromine, iodine or halides in addition to the above mentioned constituents, so that the process can be carried out in reactor systems equipped with oxidizable electrodes. By adjusting the gas flow rates or composition ratios of CHF3, SF6, and argon in the etching gas mixture, it is possible to adjust the resulting etching selectivity of silicon nitride relative to silicon oxide, and the particular edge slope angle of the etched edge of the remaining silicon nitride layer. A high etch rate for the silicon nitride is simultaneously achieved.

Integrated palladium-based micromembranes for hydrogen separation and hydrogenation/dehydrogenation reactions

Abstract: The present invention relates to gas separation membranes including a metal-based layer (17) having sub-micron scale thicknesses. The metal-based layer (17) can be a palladium alloy supported by ceramic layers such as a silicon oxide layer and a silicon nitride layer. By using MEMS, a series of perforations (holes) (11) can be patterned to allow chemical components to access both sides of the metal-based layer. Heaters and temperature sensing devices can also be patterned on the membrane (16). The present invention also relates to a portable power generation system at a chemical microreactor comprising the gas separation membrane. The invention is also directed to a method for fabricating a gas separation membrane. Due to the ability to make chemical microreactors of very small sizes, a series of reactors can be used in combination on a silicon surface to produce an integrated gas membrane device.

Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage

Abstract: A method for treating exposed surfaces of a low k carbon doped silicon oxide dielectric material in order to protect the low k carbon doped silicon oxide dielectric material from damage during removal of photoresist mask materials is described. The process comprises (a) first treating the exposed surfaces of a low k carbon doped silicon oxide dielectric material with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material and (b) then treating the semiconductor wafer with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer. These steps will prevent the degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material.

Low-energy xenon ion sputtering of ceramics investigated for stationary plasma thrusters

Abstract: The low-energy sputtering of boron nitride, magnesium oxide, boron nitride and aluminum nitride (BNAlN), and boron nitride and silicon oxide (BNSiO2) by xenon ions of bombarding energies 350, 500 eV, and 1 keV was studied experimentally. In order to measure the ion current without being significantly disturbed by slow ions, only planar probes were used during short duration sputtering experiments (of the order of 10 h). Moreover, slow ion current contribution was estimated by numerical simulations and subtracted from each ion current measurement. It was found that the ion-beam incidence effect on sputtering yields was not as important as for theoretical results or experimental results on quasinonrough solid surfaces, for which it is possible to observe a more pronounced angular dependence of the sputtering yield. This phenomenon is due to surface irregularities of ceramic materials and because of surface roughness the macroscopic sputtering yield should actually result from the convolution of the microsco...

Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines

Abstract: A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.

Synthesis of nanotubes and nanowires of silicon oxide

Abstract: Now one-dimensional structures with nanometer diameters are of great potential for testing and understanding fundamental concepts about the roles of dimensionality and size in optical, electrical, and mechanical properties and for applications in the semiconductor industry as well as mechanical and chemical areas. Since the discovery of carbon nanotubes in 1991 [1], the preparation of one-dimensional structures of nanotubes and nanowires have attracted a wide attention. In recent years, there has been intense interest surrounding the fabrication of nanotubes and wires of oxides have also been synthesized with the sol-gel template method. There are two main templates applied for producing oxide nanotubes. One involves carbon nanotubes as the template, which is coated with tetraethylorthosilicate or some other such precursor which is then oxidized. The inorganic hollow nanotubes of SiO 2, Al2O3, V2O5 and MoO3 are prepared in this way [2]. The other involves a membrane as the template, by which the inorganic nanofibers, such as TiO 2, MnO2, Co3O4, WO3 and ZnO have been formed, the desired materials being synthesized within the pores of nanoporous membranes [3, 4]. Recently, multi-element nanocables comprising multiple phases were successfully synthesized by means of laser ablation [5, 6], and many mesoporous metal oxides and hybrid hollow spheres were fabricated by the template method [7, 8]. There is currently an intensive effort to develop largescale semiconductor nanowire or nanotube materials, such as Si and silicon oxide SiO x (1< x< 2), with the uniform wide range of sizes up to 30 nm, which would open up new opportunities in the semiconductor and catalysis industries, but these structures are difficult to achieve at present. Although silica tubes with large diameter (about 1 μm) or imperfect SiO2 nanotubes have been prepared [9, 2], from the view of applications in the future, a detailed study on the macroscopic synthesis of aligned nanotubes and nanowires of silicon oxide with about 30 nm diameter will be significant. Here we report the macroscopic preparation of aligned silicon oxide nanotubes, bamboo-like nanofibers and nanowires with a uniform diameter of ∼30 nm using an ordered nanochannel-arrays of anodic alumina as templates. The ordered nanochannel-arrays of anodic alumina were prepared via the anodization of an aluminum textured pattern on the surface [10] in a 3% oxalic acidic solution under the constant-voltage condition (40 V). It is about 6μm and contains ordered cylindrical pores with the uniform diameter of 20–30 nm almost perpendicular to the film surface. The aligned silicon oxide nanostructures were prepared on this anodic alumina using a sol-gel method. At first, 52 ml of tetraethyl orthosilicate (TEOS) was added slowly into 115 ml ethanol to form TEOS solution. Secondly, 115 ml portion of ethanol were mixed with 18 ml of H 2O and 0.27 ml of HCl. Then the second solution was added slowly into TEOS solution whilst stirred in a bath to yield a silica sol at room temperature. After aging the sol for some days at room temperature or 50 ◦C, the highly ordered nanochannel-array of anodic alumina began to be dipped into the sol for 1 min, and then was removed and dried for more than 1 day. Finally, the sol-containing anodic alumina were heated in air at 200◦C for 1 day. We employed scanning electron microscopy (SEM, Jeol S500) and transmission electron microscopy (TEM, Jeol 3000F) to observe the morphology of the nanostructures obtained. For the SEM and TEM experiments, we used a chemical solution (H3PO4, CrO3 and H2O) to dissolve partly or entirely

Method for forming a hard mask of half critical dimension

Abstract: The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.

Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption

Abstract: A process is described for treating damaged surfaces of a low dielectric constant organo silicon oxide insulation layer of an integrated circuit structure to inhibit absorption of moisture which comprises treating such damaged surfaces of said organo silicon oxide insulation layer with a hydrogen plasma. The treatment with hydrogen plasma causes hydrogen to bond to silicon atoms with dangling bonds in the damaged surface of the organo silicon oxide layer to replace organic material severed from such silicon atoms at the damaged surface, whereby absorption of moisture in the damaged surface of the organo silicon oxide layer, by bonding of such silicon dangling bonds with moisture, is inhibited.

Method of manufacturing semiconductor device

Abstract: To selectively grow a P type silicon layer and a Si/GexSi1-x superlattice layer (7) under low temperature conditions in the area encircled with a groove (4), at least the side walls of which consist of silicon oxide film, which is formed in the silicon substrate. Thereby, the leak at the side of the superlattice layer can be reduced. Furthermore, by burying a metal film in the groove, the loss of light at the side of the superlattice layer (7) can be suppressed to the minimum. Thus a light receiver having silicon/germanium.silicon-mixed-crystal layer is stably formed in a silicon semiconductor substrate and optical absorption efficiency can be improved.

Method for fabricating a concave bottom oxide in a trench

Abstract: A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.

Low-temperature growth of high-integrity silicon oxide films by oxygen radical generated in high-density krypton plasma

Abstract: This paper focuses attention on the electrical properties of silicon oxide films grown by Kr-O/sub 2/ mixed high-density and low electron temperature microwave-excited plasma at 400/spl deg/C They exhibit high growth rate, high dielectric strength, high charge-to-breakdown, and low interface traps and bulk charge enough to replace thermally grown silicon oxide

In situ deposition and integration of silicon nitride in a high density plasma reactor

Abstract: A method of depositing a dielectric film on a substrate, comprising depositing a silicon oxide layer on the substrate; and treating the dielectric layer with oxygen. A layer of FSG having a fluorine content of greater than 7%, as measured by peak height ratio, deposited by HDP CVD, is treated with an oxygen plasma. The oxygen treatment stabilizes the film. In an alternative embodiment of the invention a thin (<1000 Å thick) layer of material such as silicon nitride is deposited on a layer of FSG using a low-pressure strike. The low pressure strike can be achieved by establishing flows of the process gases such that the pressure in the chamber is between 5 and 100 millitorr, turning on a bias voltage for a period of time sufficient to establish a weak plasma, which may be capacitively coupled. After the weak plasma is established a source voltage is turned on and subsequently the bias voltage is turned off. Silicon nitride layers deposited using the low pressure strike exhibit good uniformity, strong adhesion, and inhibit outgassing from underlying layers.

Method of forming a dual damascene structure on a semiconductor wafer

Abstract: The present invention provides a method of forming a dual damascene structure on a semiconductor wafer. The semiconductor wafer comprises a substrate, and a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a photoresist layer sequentially formed on the substrate. A dry-etching process is performed first to vertically remove a specific portion of the second silicon oxide layer down to the silicon nitride layer so as to form a hole. Then the photoresist layer is removed and the portion of the silicon nitride layer positioned under the hole is removed using a phosphoric acid solution. A lithographic process is then performed to form a photoresist layer on the second silicon oxide layer, the photoresist layer comprising a line-shaped opening positioned above the hole with a width larger than the diameter of the hole. Then an etching process is performed along the line-shaped opening to vertically remove the second silicon oxide layer and the first silicon oxide layer. The photoresist layer is then removed completely. Finally, a metallic layer is deposited and a CMP process is performed to form a conductive wire coupled with the via plug on the semiconductor wafer.

Low Vacuum Wafer Bonding

Abstract: Compared to bonding wafers in air, bonding of hydrophilic silicon wafers performed in low vacuum leads to much stronger bonds at the bonding interface after annealing at temperatures as low as . The bond energy reached is close to that of thermal silicon oxide itself. For hydrophilic wafer pairs bonded in air, a high bond energy at the bonding interface can also be realized by a low vacuum storage prior to the annealing, or a low vacuum annealing at after bonding. These low vacuum effects appear to be associated with a significant reduction of trapped nitrogen at the bonding interface. Trapped nitrogen prevents an intimate contact of the bonding surfaces during annealing and thus prevents formation of covalent bonds. Because a difference in thermal expansion coefficients is usually present between different wafers, in order to avoid excess thermal stresses the low vacuum bonding approach is crucial for bonding of dissimilar materials in applications such as microelectromechanical systems and has been applied to bonding silicon to materials other than silicon which have hydrophilic surfaces. ©1998 The Electrochemical Society

Mechanism of the Chemical Deposition of Nickel on Silicon Wafers in Aqueous Solution

Abstract: The deposition of metallic nickel on n-Si(100) wafers was performed without external potential control in aqueous NiSO 4 solutions of different compositions at pH 8.0. Without giving any catalyzation treatment, the deposition of nickel on hydrogen-terminated Si(100) was confirmed in a conventional electroless plating bath containing NaH 2 PO 2 as the reducing agent, sodium citrate as the complexing agent, and (NH 4 ) 2 SO 4 as the buffering agent. The deposition of nickel was found to take place also in a bath without the reducing agent, and even in a simple solution consisting of NiSO 4 and (NH 4 ) 2 SO 4 . By using a transmission electron microscope equipped with an energy dispersive X-ray spectrometer, the cross sections of the films deposited from these solutions were examined, which revealed formation of silicon oxide between the Ni deposit and Si substrate. Based on these results, the mechanism of the entire process of electroless Ni deposition on Si is discussed.

Method of fabricating a dual gate dielectric

Abstract: Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.

Method of manufacturing interconnection structural body

Abstract: Disclosed is a method for producing a circuit structure having an insulator layer comprising a porous silicon oxide thin film, which comprises (1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on a substrate, which silicon oxide-organic polymer composite thin film comprises a silicon oxide having an organic polymer dispersed therein, (2) forming, in the preliminary insulator layer, a groove which defines a pattern for a circuit, (3) forming, in the groove, a metal layer which functions as a circuit, and (4) removing the organic polymer from the preliminary insulator layer to render the preliminary insulator layer porous, thereby converting the preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film. By the method of the present invention, the capacitance between mutually adjacent circuit lines (line-to-line capacitance) in the circuit structure can be lowered.

Method of fabricating on-chip inductor

Abstract: A method of fabricating an on-chip inductor is disclosed. First, a semiconductor substrate is patterned and etched to form a trench into which an insulating layer is filled. The insulating layer is provided with a relative permitivity smaller than silicon oxide or a relative permeability greater than silicon oxide. Then, a spiral conductive coil is formed over the insulating layer.