Showing papers on "Silicon oxide published in 2001"

Graded thin films

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

High selectivity Si-rich SiON etch-stop layer

Abstract: The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC) A dual damascene structure is formed by depositing a first dielectric layer A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer A first opening is etched in the first insulating layer A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer A second dual damascene opening is etched into the dielectric layers The anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern

Surface passivation of silicon solar cells using plasma-enhanced chemical-vapour-deposited SiN films and thin thermal SiO2/plasma SiN stacks

Abstract: Two different techniques for the electronic surface passivation of silicon solar cells, the plasma-enhanced chemical vapour deposition of silicon nitride (SiN) and the fabrication of thin thermal silicon oxide/plasma SiN stack structures, are investigated. It is demonstrated that, despite their low thermal budget, both techniques are capable of giving an outstanding surface passivation quality on the low-resistivity (∼1 � cm) p-Si base as well as on n + -diffused solar cell emitters with the oxide/nitride stacks showing a much better thermal stability. Both techniques are then applied to fabricate frontand rear-passivated silicon solar cells. Open-circuit voltages in the vicinity of 670 mV are obtained with both passivation techniques on float-zone single-crystalline silicon wafers, demonstrating the outstanding surface passivation quality of the applied passivation schemes on real devices. All-SiN passivated multicrystalline silicon solar cells achieve an open-circuit voltage of 655 mV, which is amongst the highest open-circuit voltages attained on this kind of substrate material. The high open-circuit voltage of the multicrystalline silicon solar cells results not only from the excellent degree of surface passivation but also from the ability of the cell fabrication to maintain a relatively high bulk lifetime (>20 µs) due to the low thermal budget of the surface passivation process.

Method of forming graded thin films using alternating pulses of vapor phase reactants

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO 2 ) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Interfacial reactions between thin rare-earth-metal oxide films and Si substrates

Abstract: Rare-earth-metal oxide films (Ln2O3; Ln=Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Er, Tm, and Yb) between 20 and 30 nm thick were grown on Si substrates by using a pyrolysis method. We found that a silicate (LnSiO) layer and a silicon oxide layer were formed at the interface between oxides and substrate after postannealing. The infrared absorption of the Si–O–Ln bonds increased as the postannealing temperature rose. The Si–O–Ln bond formation strongly depended on the ion radii of the rare-earth elements. We conclude that an interfacial silicate layer can easily be formed by a reaction with Si atoms diffusing from the substrate for oxides with larger ion radii. This is because such oxides may have a larger space between atoms. The quantity of Si–O–Si bonds also increased after postannealing. The increase in the Si–O–Si bonds for Ln2O3 was independent of the elements, and almost the same as the increases for Ta2O5 and ZrO2.

Surface recombination velocity of phosphorus-diffused silicon solar cell emitters passivated with plasma enhanced chemical vapor deposited silicon nitride and thermal silicon oxide

Abstract: This work was supported by funding from the Australian Research Council. One of the authors ~J.S.! gratefully acknowledges the support of a Feodor Lynen fellowship by the Alexander von Humboldt Foundation of Germany.

Process for forming a low dielectric constant carbon-containing film

Abstract: An embodiment of the present invention provides methods for forming a carbon-containing layer having a low dielectric constant and good gap-fill capabilities. A method includes depositing a carbon-containing layer on a substrate and transforming the carbon-containing layer to remove at least some of the carbon. The transforming step may include annealing the carbon-containing layer in a furnace containing a hydrogen atmosphere, for example. The carbon-containing layer may be a carbon-doped silicon oxide material, where the transforming step changes the carbon-doped silicon oxide. Additionally, the method may include subjecting the annealed layer to a hydrogen and/or low oxygen plasma treatment to further remove carbon from the layer. Additionally, a step of adding a capping layer to the annealed, plasma treated material is provided. Products made by the above methods are also included, such as a product including a low k carbon-containing layer where the low k carbon-containing layer has been transformed to remove some of the carbon from the layer. An additional product includes a transformed carbon-containing layer further subjected to a hydrogen plasma treatment to remove more carbon from the layer. Further, a capping layer deposited over the transformed and hydrogen plasma treated layer is provided.

Hydrogen assisted undoped silicon oxide deposition process for HDP-CVD

Abstract: A method of forming a silicon oxide layer over a substrate disposed in a high density plasma substrate processing chamber. The silicon oxide layer is formed by flowing a process gas including a silicon-containing source, an oxygen-containing source, an inert gas and a hydrogen-containing source into the substrate processing chamber and forming a high density plasma (i.e., a plasma having an ion density of at least 1×1011 ions/cm3) from the process gas to deposit said silicon oxide layer over said substrate. In one embodiment, the hydrogen-containing source in the process gas is selected from the group of H2, H2O, NH3, CH4 and C2H6.

Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput

Abstract: Embodiments of the present invention include a method of depositing an improved seasoning film. In one embodiment the method includes, prior to performing a substrate processing operation, forming a layer of silicon over an interior surface of the substrate processing chamber as opposed to a layer of silicon oxide. In certain embodiments, the layer of silicon comprises at least 70% atomic silicon, is deposited from a high density silane (Si n H 2n+2 ) process gas and/or is deposited from a plasma having a density of at least 1×10 11 ions/cm 3 .

Optical gain at 1.54 μm in erbium-doped silicon nanocluster sensitized waveguide

Abstract: Optical gain at 1.54 μm in erbium-doped silicon-rich silicon oxide (SRSO) is demonstrated. Er-doped SRSO thin film was fabricated by electron-cyclotron resonance enhanced chemical vapor deposition of silicon suboxide with concurrent sputtering of erbium followed by a 5 min anneal at 1000 °C. Ridge-type single mode waveguides were fabricated by wet chemical etching. Optical gain of 4 dB/cm of an externally coupled signal at 1.54 μm is observed when the Er is excited via carriers generated in the Si nanoclusters by the 477 nm line of an Ar laser incident on the top of the waveguide at a pump power of 1.5 W cm−2.

Method for forming a high dielectric constant material

Abstract: Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.

Method of fabricating semiconductor device

Abstract: According to the inventive method of fabricating a semiconductor device, a silicon substrate is exposed to an oxygen atmosphere of 600° C. to 900° C., for forming silicon oxide films on surfaces of epitaxial silicon layers and those of silicon fragments. Thus, a method of fabricating a semiconductor device capable of preventing electrodes thereof from shorting can be provided.

Semiconductor integrated circuit device and manufacturing method thereof

Abstract: After a silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in the region in which a gate insulating film having a small effective thickness is to be formed is removed with an aqueous solution of hydrofluoric acid, and an insulating film (10) of a high dielectric constant is then formed over the semiconductor substrate (1). Thus, over this semiconductor substrate (1), there are formed two gate insulating films: a gate insulating film (12) formed of a multilayer film of the high-dielectric constant insulating film (10) and the silicon oxide film (9); and a gate insulating film (11) of the high-dielectric constant insulating film (10).

Composite microelectronic dielectric layer with inhibited crack susceptibility

Abstract: Within each of a pair of methods for forming each of a pair of microelectronic fabrications with reduced cracking within each of a pair of silicon oxide dielectric layers there is employed at least one stress reducing layer. The at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material, such as a silicon nitride dielectric material or a silicon oxynitride dielectric material.

Process for selectively etching dielectric layers

Abstract: A method is provided for etching a dielectric structure. The dielectric structure comprises: (a) a layer of undoped silicon oxide or F-doped silicon oxide; and (b) a layer of C,H-doped silicon oxide. The dielectric structure is etched in a plasma-etching step, which plasma-etching step is conducted using a plasma source gas that comprises nitrogen atoms and fluorine atoms. As one example, the plasma source gas can comprise a gaseous species that comprises one or more nitrogen atoms and one or more fluorine atoms (e.g., NF3). As another example, the plasma source gas can comprise (a) a gaseous species that comprises one or more nitrogen atoms (e.g., N2) and (b) a gaseous species that comprises one or more fluorine atoms (e.g., a fluorocarbon gas such as CF4). In this etching step, the layer of C,H-doped silicon oxide is preferentially etched relative to the layer of undoped silicon oxide or F-doped silicon oxide. The method of the present invention is applicable, for example, to dual damascene structures.

Infrared spectroscopy study of low-dielectric-constant fluorine-incorporated and carbon-incorporated silicon oxide films

Abstract: Bonding characteristics of low-dielectric-constant (low-k) fluorine-incorporated silicon oxide (SiOF) and carbon-incorporated silicon oxide (SiOC) films prepared by plasma enhanced chemical vapor deposition were investigated by Fourier transform infrared spectroscopy (FTIR). The frequency of Si–O stretching vibration mode in SiOF film shifted to higher wave number (blueshift) with the increase of fluorine incorporation, while that in SiOC film shifted to lower wave number (redshift) as the carbon content increased. In N2-annealed SiOC film, the Si–O stretching frequency slightly shifted to lower wave number. To elucidate these phenomena, we have developed the “bonding structure model” based on the electronegativity of an atom. The frequency shifts observed in the FTIR spectra of SiOF and SiOC films were well explained by this model.

In situ dielectric stacks

Abstract: Multiple sequential processes are conducted in situ in a single-wafer processing chamber, particularly for forming ultrathin dielectric stacks of high quality. The chamber exhibits single-pass, laminar gas flow, facilitating safe and clean sequential processing. Furthermore, a remote plasma source widens process windows, permitting isothermal sequential processing and thereby reducing the transition time for temperature ramping between in situ steps. In exemplary processes, extremely thin interfacial silicon oxide, nitride and/or oxynitride is grown, followed by in situ silicon nitride deposition. Cleaning, anneal and electrode deposition can also be conducted in situ, reducing transition time without commensurate loss in reaction rates.

Method to improve adhesion of organic dielectrics in dual damascene interconnects

Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

Method of forming insulation layer in semiconductor devices for controlling the composition and the doping concentration

Abstract: The present invention relates to a method of forming an insulating film in a semiconductor device by which the composition and the doping concentration of oxide are controlled using an atomic layer deposition method. In case of silicon oxide, a thermal oxidization process and a deposition process are sequentially performed to form an oxide film having a good interface characteristic and the deposition speed. On the other hand, in case of depositing an oxide film, an oxynitride film and a metal oxide film, the pulse construction and the supply time of a source and radical are adjusted to form an optimum oxide film having a good interface characteristic.

Method of improving moisture resistance of low dielectric constant films

Abstract: A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10W to about 500W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.

Extraordinary elevation of the glass transition temperature of thin polymer films grafted to silicon oxide substrates

Abstract: We used local thermal analysis and ellipsometry to measure the glass transition temperatures (Tg) of supported thin films of poly(4-hydroxystyrene) (PHS) and hydroxy terminated polystyrene (PS-OH). The films were spuncast from solution onto silicon oxide substrates and annealed under vacuum at elevated temperatures to graft the polymer to the substrate. Grafting was verified and characterized in terms of the thickness of and the advancing contact angle of water on the residual layer after solvent extraction. For PHS, each segment of the polymer chain was capable of grafting to the substrate. The thickness of the residual layer increased with increasing annealing temperature. For this polymer the critical thickness below which the Tg of the film deviated from the bulk value was nearly 200 nm after annealing at the highest temperature (190 °C); the Tg of films 100 nm thick or less were elevated by more than 50 °C above the bulk value. For PS-OH films the polymer was only capable of grafting at one chain end...

Transient conduction in multidielectric silicon–oxide–nitride–oxide semiconductor structures

Abstract: The voltage- and time-dependence of the tunneling currents in polysilicon–oxide–nitride–oxide semiconductor structures have been investigated. Electron and hole contributions were separated using a shallow junction technique. The standard tunneling model for charge injection was successfully applied to describe the observed threshold voltage shifts. For both positive and negative gate voltages, the time-dependence of the current density through the tunneling oxide is given by a simple analytical equation. This equation is characterized by an initial time constant and an asymptotic t−1-dependence. At large programming times the current density follows the t−1-dependence, independent of the tunneling oxide thickness and applied voltage. Under positive polarity (write) electrons are injected from the substrate. Under negative polarity (erase) and previous injection electron back-tunneling rather than hole injection is dominant at the beginning of erasing. At the end of erasing, steady-state conduction can be...

Semiconductor device and method of producing the same

Abstract: A dummy gate electrode is formed before the gate electrode is formed. Extension regions, side wall silicon nitride film, source/drain regions, silicon oxide film, and others are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused to a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method gives a semiconductor device that prevents the deterioration of electrical characteristics caused by short channel effect and parasitic resistance.

Method for forming dielectric stack without interfacial layer

Abstract: A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

Atomic Layer Deposition of High Dielectric Constant Nanolaminates

Abstract: Thin stacks comprised of alternating layers of Ta 2 O 5 /HfO 2 , Ta 2 O 5 /ZrO 2 , and ZrO 2 /HfO 2 were investigated as high-permittivity insulators for possible gate dielectric applications These thin layers were deposited on silicon substrates using atomic layer deposition. Nanolaminates with silicon oxide equivalent thickness of about 2 nm had dielectric constants of around ten and leakage current densities at 1 MV/cm of around 10 -8 A/cm 2 . Of the three kinds of nanolaminates investigated. ZrO 2 /HfO 2 structures showed the highest breakdown field and the lowest leakage current.

Characterization of electroless deposited Co(W,P) thin films for encapsulation of copper metallization

Abstract: Thin Co(W,P) films, 100–200 nm thick, were electroless deposited on oxidized silicon wafers using sputtered copper or cobalt as catalytic seed layers. The purpose of these films is to encapsulate copper preventing its corrosion or to serve as a diffusion barrier against copper contamination of silicon oxide and silicon in ULSI interconnect and packaging applications. The electroless cobalt layers were integrated with electroless copper and found to function as barriers up to a temperature of 500°C. The microstructure of the barrier film was found to consist of grains of h.c.p. cobalt, ∼10 nm in diameter, in which the grain boundaries are most probably enriched by phosphorus and tungsten. It was found that the phosphorus and tungsten impurities stabilize the h.c.p. phase, postponing the transition to the f.c.c. phase by more than 80°C, compared to pure bulk cobalt. The observed good barrier properties can be explained by the nano-sized grains along with the blocking effect of the impurities at the fast diffusion path of the grain boundaries. An advantage of these layers, relative to alternative diffusion barriers for copper, is their low electrical resistivity, 40 μΩ cm.

Evidence of light-emitting amorphous silicon clusters confined in a silicon oxide matrix

Abstract: Amorphous silicon oxide thin films were prepared by the coevaporation technique in ultrahigh vacuum. Different compositions were obtained by changing the evaporation rate of silicon. The samples were then annealed to different temperatures up to 950 °C. The composition and the structure were investigated using energy dispersive x-ray spectroscopy, infrared absorption measurements, and Raman spectroscopy. This study attests the presence of amorphous silicon clusters in a silicon oxide matrix. Optical transmission measurements were performed and interpreted in the field of the composite medium theory. The obtained results are in good agreement with the presented structural model. The photoluminescence in the red-orange domain was studied in relation with the structure. The correlation between the photoluminescence energy and intensity and the structure shows that the light emission originates from the silicon clusters embedded in the silicon oxide matrix. Moreover the dependence of the photoluminescence energy with the silicon volume fraction suggests the origin of the light emission could be due to a quantum confinement effect of carriers in the amorphous silicon clusters.