Showing papers on "Silicon oxide published in 2002"

Silicon Oxide Nafion Composite Membranes for Proton-Exchange Membrane Fuel Cell Operation at 80-140°C

Abstract: Silicon oxide/Nafion composite membranes were studied for operation in hydrogen/oxygen proton-exchange membrane fuel cells (PEMFCs) from 80 to 140°C. The composite membranes were prepared either by an impregnation of Nafion 115 via sol-gel processing of tetraethoxysilane or by preparing a recast film, using solubilized Nafion 115 and a silicon oxide polymer/gel Tetraethoxysilane, when reacted with water in an acidic medium, undergoes polymerization to form a mixture of SiO 2 and siloxane polymer with product hydroxide and ethoxide groups. This material is referred to as SiO s /-OH/-OEt. When Nafion is used as the acidic medium, the SiO 2 /siloxane polymer forms within the membrane. All composite membranes had a silicon oxide content of less than or equal to 10 wt %. The silicon oxide improved the water retention of the composite membranes, increasing proton conductivity at elevated temperatures Attenuated total reflectance-Fourier transform infrared spectroscopy and scanning electron microscopy experiments indicated an evenly distributed siloxane polymer of SiO 2 /-OH/-OEt in the composite membranes. At a potential of 0.4 V, silicon oxide/Nafion 115 composite membranes delivered four times the current density obtained with unmodified Nafion 115 in a H 2 /O 2 PEMFC at 130°C and a pressure of 3 atm. Furthermore, silicon oxide-modified membranes were more robust than the control membranes (unmodified Nafion 115 and recast Nafion), which degraded after high operation temperature and thermal cycling.

Polymer thin-film transistors with chemically modified dielectric interfaces

Abstract: The characteristics of polymeric thin-film transistors can be controlled by chemically modifying the surface of the gate dielectric prior to the deposition of the organic semiconductor. The chemical treatment consists of derivatizing the silicon oxide surface with organic trichlorosilanes to form self-assembled monolayers (SAMs). The deposition of an octadecyltrichlorosilane SAM leads to a mobility of 0.01–0.02 cm2/V s in a polyfluorene copolymer, a 20-fold improvement over the mobility on bare silicon oxide. The mobility enhancement mechanism is likely to involve molecular interactions between the polymer and the SAM.

Very low bulk and surface recombination in oxidized silicon wafers

Abstract: Bulk and surface processes determine the recombination rate in crystalline silicon wafers. In this paper we report effective lifetime measurements for a variety of commercially available float-zone silicon wafers that have been carefully passivated using alnealed silicon oxide. Different substrate resistivities have been explored, including both p-type (boron) and n-type (phosphorus) dopants. Record high effective lifetimes of 29 and 32 ms have been measured for 90 Ω cm n-type and 150 Ω cm p-type silicon wafers, respectively. The dependence of the effective lifetime has been measured for excess carrier densities in the range of 1012–1017 cm−3. These results demonstrate that very low bulk and surface recombination rates can be maintained during high-temperature oxidation (1050 °C) by carefully optimizing the processing conditions.

Helical Crystalline SiC/SiO2 Core−Shell Nanowires

Abstract: Helical crystalline silicon carbide nanowires covered with a silicon oxide sheath (SiC/SiO2) have been synthesized by a chemical vapor deposition technique. The SiC core typically has diameters of 10-40 nm with a helical periodicity of 40-80 nm and is covered by a uniform layer of 30-60 nm thick amorphous SiO2. A screw-dislocation-driven growth process is proposed for the formation of this novel structure based on detailed structural characterizations. The helical nanostructures may find applications as building blocks in nanomechanical or nanoelectronic devices. The screw-dislocation-induced growth mechanism suggests that similar helical nanostructures of a wide range of materials may be synthesized.

Silicon oxide film formation method

Abstract: An object of this invention is to provide a silicon oxide film formation method capable of enhancing efficiency for generating atomic oxygen and improving film quality of a silicon film (SiO 2 film) in forming the silicon oxide film using an RS-CVD system. This object is attained by adding nitrogen atom containing gas (N 2 gas, NO gas, N 2 O gas, NO 2 gas or the like) to oxygen atom containing gas (O 2 gas, O 3 gas or the like) introduced into a plasma generating space in the vacuum container to produce plasmas by these gases and to thereby increase the quantity of the atomic oxygen generated by the plasmas in the plasma generating space.

Etch process for dielectric materials comprising oxidized organo silane materials

Abstract: The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016) and wider trenches. The technique is also suitable for forming dual damascene structures In additional embodiments, manufacturing systems are provided for fabricating IC structures of the present invention. These systems include a controller that is adapted for interacting with a plurality of fabricating stations.

Raman scattering and photoluminescence from Si nanoparticles in annealed SiOx thin films

Abstract: Silicon-rich silicon oxide thin films have been prepared by thermal evaporation of silicon monoxide in vacuum. The SiOx film composition (1.1⩽ x ⩽1.7) has been controlled by varying the deposition rate and residual pressure in the chamber. Long time stability of all films has been ensured by a postdeposition annealing at 523 K for 30 min in Ar atmosphere. Some films were further annealed at 973 K and some others at 1303 K. Raman scattering measurements have implied the formation of amorphous silicon nanoparticles in films annealed at 973 K and Si nanocrystals in films annealed at 1303 K. The latter conclusion is strongly supported by high resolution electron microscopy studies which show a high density of Si nanocrystals in these films. Photoluminescence has been observed from both amorphous and crystalline nanoparticles and interpreted in terms of band-to-band recombination in the nanoparticles having average size greater than 2.5 nm and carrier recombination through defect states in smaller nanoparticles.

Fabrication method of semiconductor integrated circuit device

Abstract: The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves, or the silicon carbide film or the organic insulating film exposed to the side walls of the interconnection grooves are side-etched When a lamination film made of a silicon oxide film, an organic insulating film, a silicon oxide film, an organic insulating film and a silicon carbide film is dry-etched to form interconnection grooves over Cu interconnections, a mixed gas of SF 6 and NH 3 is used as an etching gas for the silicon carbide film to work side walls of the interconnection grooves perpendicularly and further suppress defects that a deposit or a reactant adheres to the surface of the Cu interconnections exposed to the bottom of the interconnection grooves

ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS

Abstract: A dielectric film containing a nanolaminate with a hafnium oxide layer and a zirconium oxide layer and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using silicon oxide.

Combined gate cap or digit line and spacer deposition using HDP

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Synthesis of Ultra‐Long and Highly Oriented Silicon Oxide Nanowires from Liquid Alloys

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Etch process for etching microstructures

Abstract: A two-step method of releasing microelectromechanical devices from a substrate is disclosed. The first step comprises isotropically etching a silicon oxide layer sandwiched between two silicon-containing layers with a gaseous hydrogen fluoride-water mixture, the overlying silicon layer to be separated from the underlying silicon layer or substrate for a time sufficient to form an opening but not to release the overlying layer, and the second step comprises adding a drying agent to substitute for moisture remaining in the opening and to dissolve away any residues in the opening that can cause stiction.

Multiple precursor cyclical deposition system

Abstract: Embodiments of the present invention relate to an apparatus and method of cyclical deposition utilizing three or more precursors in which delivery of at least two of the precursors to a substrate structure at least partially overlap. One embodiment of depositing a ternary material layer over a substrate structure comprises providing at least one cycle of gases to deposit a ternary material layer. One cycle comprises introducing a pulse of a first precursor, introducing a pulse of a second precursor, and introducing a pulse of a third precursor in which the pulse of the second precursor and the pulse of the third precursor at least partially overlap. In one aspect, the ternary material layer includes, but is not limited to, tungsten boron silicon (WBxSiy), titanium silicon nitride (TiSixNy), tantalum silicon nitride (TaSixNy), silicon oxynitride (SiOxNy), and hafnium silicon oxide (HfSixOy). In one aspect, the composition of the ternary material layer may be tuned by changing the flow ratio of the second precursor to the third precursor between cycles.

Moving beyond molecules: Patterning solid-state features via dip-pen nanolithography with sol-based inks

Abstract: Herein, we described a new dip-pen nanolithography (DPN)-based method for the direct patterning of organic/inorganic composite nanostructures on silicon and oxidized silicon substrates. The approach works by the hydrolysis of metal precursors in the meniscus between an AFM tip and a surface according to the reaction 2MCln + nH2O → M2On + 2nHCl; M = Al, Si, and Sn. The inks are hybrid composites of inorganic salts with amphiphilic block copolymer surfactants. Three proof-of-concept systems involving Al2O3, SiO2, and SnO2 nanostructures on silicon and silicon oxide surfaces have been studied. Arrays of dots and lines can be written easily with control over feature size and shape on the sub-200 nm level. The structures have been characterized by atomic force microscopy, scanning electron microscopy, transmission electron microscopy, and energy-dispersive X-ray analysis. This work is important because it opens up the opportunity for using DPN to deposit solid-state materials rather than simple organic molecul...

Coated article with anti-reflective layer(s) system

Abstract: Coated articles are provided with an anti-reflective (AR) layer(s) system which enables reduced reflection, increased visible transmission, and/or neutral color. In certain embodiments, the AR layer(s) system includes a silicon nitride layer(s), a silicon oxynitride layer, and/or a silicon oxide layer on the substrate over an infrared (IR) reflecting layer(s) such as silver. The AR system surprisingly enables improved visible transmission and/or reflection to be combined with more neutral color.

Semiconductor device and method of manufacturing same

Abstract: Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist ( 25 ) is formed so as to cover a low voltage operation region (A 2 ), a second LDD implantation process of implanting an impurity ion ( 14 ) by using the resist ( 25 ) as a mask, is performed over a silicon oxide film ( 6 ) thereby to form an impurity diffusion region ( 13 ) in the surface of a semiconductor substrate ( 1 ) in a high voltage operation region (A 1 ). After this step, the silicon oxide film ( 6 ) in the high voltage operation region (A 1 ) contains the impurity during the second LDD implantation process whereas the silicon oxide film ( 6 ) in a low voltage operation region (A 2 ) contains no impurity. This leads to such a characteristic that in the following pre-treatment with a wet process, the silicon oxide film ( 6 ) containing the impurity in the high voltage operation region (A 1 ) is reduced in thickness, and the silicon oxide film ( 6 ) containing no impurity in the low voltage operation region (A 2 ) is not reduced in thickness.

Method of manufacturing semiconductor device

Abstract: A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed is provided. A silicon oxide film (4), a polysilicon film (5) and a silicon oxide film (6) are formed in the order named on a silicon substrate (1). Then, the silicon oxide film (6) is patterned to form silicon oxide films (14a, 14b). Next, a photoresist (15) is applied, and is then exposed to light using a photomask (18) for defining the ends of gate structures (25i-25k) as seen in a direction of a gate width. Next, the photoresist (15) is developed to form openings (21s-21u). Using the photoresist (15) as an etch mask, portions of the silicon oxide films (14a, 14b) exposed in the openings (21s-21u) are etched away.

Silicon Oxynitride A Versatile Material for Integrated Optics Applications

Abstract: Silicon oxynitride is a very attractive material for integrated optics application, because of its excellent optical properties (~e.g. optical loss below 0.2 dB/cm!, the large refractive index range ~between 1.45 for silicon oxide and 2.0 for silicon nitride), and last but not least, the availability of reliable, low-cost fabrication technologies. Since good uniformity and reproducibility of the layers is extremely important for integrated optics applications, we have optimized the plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition technologies of silicon oxynitride with respect to these requirements. Over a 50x50 mm area on a 3 inch wafer, an inhomogeneity of the refractive index of Dn<5E-3 and a nonuniformity of the layer thickness of < 1% can be obtained. Furthermore, new challenges such as the conditioning of the reactor, in order to guarantee process reproducibility in the same order of magnitude, are discussed. The high optical loss of silicon oxynitride in the third telecommunication window (wavelength range 1530-1605 nm), which is caused by the overtones of the Si-H and N-H bonds, was decreased by thermal treatment. Silicon oxynitride waveguides having a refractive index of 1.48 and an optical loss below 0.2 dB/cm (at 1550 nm) were realized.

Coefficient determination related to optical gain in erbium-doped silicon-rich silicon oxide waveguide amplifier

Abstract: Gain-determining coefficients in Er-doped, nanocrystal-Si (nc-Si) sensitized silica waveguide amplifiers are investigated. Single-mode, Er-doped silica waveguides with nc-Si embedded in them were prepared by electron cyclotron resonance plasma-enhanced chemical vapor deposition of Er-doped a-Si:Ox (x<2) followed by a high-temperature anneal to precipitate nc-Si. Exciting the Er ions via nc-Si by pumping the waveguide from the top with the 477 nm line of an Ar laser resulted in an enhancement of the transmitted 1535 nm signal of up to 14 dB/cm, indicating a possible net gain of up to 7 dB/cm. From the dependence of the signal enhancement upon the pump power, an emission cross section of 2×10−19 cm2 at 1535 nm and an effective excitation cross section of ⩾10−17 cm2 at 477 nm is obtained.

Semiconductor device and method of manufacturing the same

Abstract: The present invention provides a semiconductor device including a silicon substrate; a heat insulating layer including a silicon oxide film; and a heat detecting portion, in which the heat insulating layer includes a closed cavity and/or a hole, an interior of the hole has a greater diameter than an opening of the hole, and at least a portion of the closed cavity or the hole is formed within the silicon oxide film. The invention also provides a method of manufacturing this semiconductor device.

Heat treatment apparatus and cleaning method of the same

Abstract: A semiconductor water is contained in a reaction tube, and the reaction tube is exhausted through an exhaust pipe while supplying ammonia and dichlorosilane into the reaction tube. A silicon nitride film is deposited on an object to be heat-treated by a reaction of ammonia and dichlorosilane. Subsequently, TEOS is supplied into the reaction tube, while the reaction tube is exhausted through the exhaust pipe. A silicon oxide film is deposited on the object by resolving the TEOS. A semiconductor wafer an which a laminated layer of the silicon nitride film and the silicon oxide film is formed is unloaded from the reaction tube. Then, reactive products attached into the exhaust pipe and the reaction tube are removed, by conducting fluoride hydrogen thereinto, thereby cleaning the pipers The top end of the exhaust pipe is split into two vents, either one of which is used for discharging exhaust gas for forming films and the other one of which is used for discharging HF gas for cleaning the pipes.

Silicide-silicon oxide-semiconductor antifuse device and method of making

Abstract: An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.

Metalorganic chemical vapor deposition of aluminum oxide on Si: Evidence of interface SiO2 formation

Abstract: Thin films of aluminum oxide were deposited on H-passivated Si(100) substrate using trimethylaluminum and oxygen at 0.5 Torr and 300 °C. Fourier transform infrared (FTIR) and x-ray photoelectron spectroscopic analyses of these films showed no aluminum silicate phase at the film–substrate interface. The O/Al ratio in the deposited film was found to be higher than that in stoichiometric Al2O3. On annealing the as-deposited samples in Ar at 900 °C, an absorption peak due to the transverse optical phonon for the Si–O–Si stretching mode appeared in the FTIR spectra. A combination of Z-contrast imaging and electron energy-loss spectroscopy in the scanning transmission electron microscope confirmed that the annealed samples developed a layer of silicon dioxide at the aluminum oxide–Si interface. Our results suggest that excess oxygen present in the deposited film reacts with the underlying Si substrate and forms silicon oxide.

Synthesis and photoluminescence properties of amorphous SiOx nanowires

Abstract: Silicon oxide nanowires (SiONWs) have been synthesized on a Si substrate by the vapor transport reaction using pure silicon (99.99%) powder as the Si source with the help of a Au catalyst synthesized by chemical methods. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) observations show that the amorphous SiONWs have lengths up to several tens of micrometers and diameters of ca. 20 nm. Energy dispersive X-ray spectrometry (EDX) analysis reveals that the SiONWs consist of Si and O elements in an atomic ratio of approximately 1∶1.2. The formation process of these nanowires is closely related to the vapor–liquid–solid (VLS) growth mechanism. A blue light emission was observed which could be attributed to neutral oxygen vacancies formed in the nanowires.

Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer

Abstract: Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a hard mask layer formed upon the dielectric layer. The hard mask layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency power of from about 100 to about 500 watts per square centimeter substrate area. The hard mask layer provides for attenuated abrasive damage to the dielectric layer.

Semiconductor integrated circuit device and a method of manufacturing the same

Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.

Method for increasing the capacitance in a storage trench

Abstract: In a method for forming a trench capacitor a first layer of silicon oxide is deposited in a storage trench and a layer of silicon is deposited over the first layer by a chemical vapor deposition process. A layer of an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of the oxidizable metal are subsequently oxidized to form a layer of silicon oxide and metal oxide.