Showing papers on "Silicon oxide published in 2014"

Understanding the role of underlayers and overlayers in thin film hematite photoanodes

Abstract: Recent research on photoanodes for photoelectrochemical water splitting has introduced the concept of under- and overlayers for the activation of ultrathin hematite films. Their effects on the photocatalytic behavior were clearly shown; however, the mechanism is thus far not fully understood. Herein, the contribution of each layer is analyzed by means of electrochemical impedance spectroscopy, with the aim of obtaining a general understanding of surface and interface modifications and their influence on the hematite photoanode performance. This study shows that doping of the hematite from the underlayer and surface passivation from annealing treatments and an overlayer are key parameters to consider for the design of more efficient iron oxide electrodes. Understanding the contribution of these layers, a new design for ultrathin hematite films employing a combination of a gallium oxide overlayer with thin niobium oxide and silicon oxide underlayers is shown to achieve a photocurrent onset potential for the photoelectrochemical oxidation of water more negative than 750 mV versus the reversible hydrogen electrode (RHE) at pH 13.6, utilizing Co-Pi as a water oxidation catalyst. It is demonstrated that multilayer hematite thin film photoanodes are a strategy to reduce the overpotential for this material, thereby facilitating more efficient tandem cells.

Finfet devices with unique fin shape and the fabrication thereof

Abstract: A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

Methods for forming doped silicon oxide thin films

Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.

Efficient and sustained photoelectrochemical water oxidation by cobalt oxide/silicon photoanodes with nanotextured interfaces.

Abstract: Plasma-enhanced atomic layer deposition of cobalt oxide onto nanotextured p+n-Si devices enables efficient photoelectrochemical water oxidation and effective protection of Si from corrosion at high pH (pH 13.6). A photocurrent density of 17 mA/cm2 at 1.23 V vs RHE, saturation current density of 30 mA/cm2, and photovoltage greater than 600 mV were achieved under simulated solar illumination. Sustained photoelectrochemical water oxidation was observed with no detectable degradation after 24 h. Enhanced performance of the nanotextured structure, compared to planar Si, is attributed to a reduced silicon oxide thickness that provides more intimate interfacial contact between the light absorber and catalyst. This work highlights a general approach to improve the performance and stability of Si photoelectrodes by engineering the catalyst/semiconductor interface.

Soft landing nanolaminates for advanced patterning

Abstract: Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power.

Low temperature gas-phase carbon removal

Abstract: A method of etching carbon films on patterned heterogeneous structures is described and includes a gas phase etch using remote plasma excitation. The remote plasma excites a fluorine-containing precursor and an oxygen-containing precursor, the plasma effluents created are flowed into a substrate processing region. The plasma effluents etch the carbon film more rapidly than silicon, silicon nitride, silicon carbide, silicon carbon nitride and silicon oxide.

Amorphous silicon oxide window layers for high-efficiency silicon heterojunction solar cells

Abstract: In amorphous/crystalline silicon heterojunction solar cells, optical losses can be mitigated by replacing the amorphous silicon films by wider bandgap amorphous silicon oxide layers. In this article, we use stacks of intrinsic amorphous silicon and amorphous silicon oxide as front intrinsic buffer layers and show that this increases the short-circuit current density by up to 0.43 mA/cm2 due to less reflection and a higher transparency at short wavelengths. Additionally, high open-circuit voltages can be maintained, thanks to good interface passivation. However, we find that the gain in current is more than offset by losses in fill factor. Aided by device simulations, we link these losses to impeded carrier collection fundamentally caused by the increased valence band offset at the amorphous/crystalline interface. Despite this, carrier extraction can be improved by raising the temperature; we find that cells with amorphous silicon oxide window layers show an even lower temperature coefficient than referenc...

Excellent c-Si surface passivation by low-temperature atomic layer deposited titanium oxide

Abstract: In this work, we demonstrate that thermal atomic layer deposited (ALD) titanium oxide (TiOx) films are able to provide a—up to now unprecedented—level of surface passivation on undiffused low-resistivity crystalline silicon (c-Si). The surface passivation provided by the ALD TiOx films is activated by a post-deposition anneal and subsequent light soaking treatment. Ultralow effective surface recombination velocities down to 2.8 cm/s and 8.3 cm/s, respectively, are achieved on n-type and p-type float-zone c-Si wafers. Detailed analysis confirms that the TiOx films are nearly stoichiometric, have no significant level of contaminants, and are of amorphous nature. The passivation is found to be stable after storage in the dark for eight months. These results demonstrate that TiOx films are also capable of providing excellent passivation of undiffused c-Si surfaces on a comparable level to thermal silicon oxide, silicon nitride, and aluminum oxide. In addition, it is well known that TiOx has an optimal refractive index of 2.4 in the visible range for glass encapsulated solar cells, as well as a low extinction coefficient. Thus, the results presented in this work could facilitate the re-emergence of TiOx in the field of high-efficiency silicon wafer solar cells.

Dopant etch selectivity control

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

Plasma pre-clean module and process

Abstract: A method for integrated circuit fabrication can include removing silicon oxide by a pre-clean process. The pre-clean process can include depositing a halogen-containing material on the surface of a substrate in a first reaction chamber, and transferring the substrate having the halogen-containing material to a second reaction chamber. Silicon oxide material can be removed from a surface of the substrate by sublimating the halogen-containing material in the second reaction chamber. A target material, such as a conductive material, may subsequently be deposited on the substrate surface in the second reaction chamber.

Highly selective doped oxide removal method

Abstract: A method of etching doped silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using partial remote plasma excitation. The remote plasma excites a fluorine-containing precursor and the plasma effluents created are flowed into a substrate processing region. A hydrogen-containing precursor, e.g. water, is concurrently flowed into the substrate processing region without plasma excitation. The plasma effluents are combined with the unexcited hydrogen-containing precursor in the substrate processing region where the combination reacts with the doped silicon oxide. The plasmas effluents react with the patterned heterogeneous structures to selectively remove doped silicon oxide.

Titanium oxide etch

Abstract: Methods of selectively etching titanium oxide relative to silicon oxide, silicon nitride and/or other dielectrics are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and/or a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium oxide. The plasmas effluents react with exposed surfaces and selectively remove titanium oxide while very slowly removing other exposed materials. A direction sputtering pretreatment is performed prior to the remote plasma etch and enables an increased selectivity as well as a directional selectivity. In some embodiments, the titanium oxide etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.

Plasma-free metal etch

Abstract: Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium, silicon carbide, silicon carbon nitride and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. No plasma excites the halogen-containing precursor either remotely or locally in embodiments.

Flash gate air gap

Abstract: Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.

Integrated oxide and nitride recess for better channel contact in 3D architectures

Abstract: Methods of etching back an oxide-nitride-oxide (ONO) layer of a 3-d flash memory cell without breaking vacuum are described. The methods include recessing the two outer silicon oxide dielectric layers to expose the flanks of the thin silicon nitride layer. The silicon nitride layer is then etched back from all exposed sides to hasten the process on the same substrate processing mainframe. Both etching back the silicon oxide and etching back the silicon nitride use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The process may also be reversed such that the silicon nitride is etched back first.

Role of Surface Oxides in the Formation of Solid-Electrolyte Interphases at Silicon Electrodes for Lithium-Ion Batteries

Abstract: Nonaqueous solvents in modern battery technologies undergo electroreduction at negative electrodes, leading to the formation of a solid–electrolyte interphase (SEI). The mechanisms and reactions leading to a stable SEI on silicon electrodes in lithium-ion batteries are still poorly understood. This lack of understanding inhibits the rational design of electrolyte additives, active material coatings, and the prediction of Li-ion battery life in general. We prepared SEI with a common nonaqueous solvent (LiPF6 in PC and in EC/DEC 1:1 by wt %) on silicon oxide and etched silicon (001) surfaces in various states of lithiation to understand the role of surface chemistry on the SEI formation mechanism and SEI structure. Anhydrous and anoxic techniques were used to prevent air and moisture contamination of prepared SEI films, allowing for more accurate characterization of SEI chemical stratification and composition by X-ray photoelectron spectroscopy (XPS) and time-of-flight secondary ion mass spectrometry (TOF-S...

Feol low-k spacers

Abstract: Transistors and their methods of formation are described. Low dielectric constant material (e.g. a void) is placed between an elongated gate and a contact to increase the attainable switching speed of the gate of the device. An elongated structural slab of silicon nitride is temporarily positioned on both sides of the gate. Silicon oxide is formed over the silicon nitride slabs and the gate. Contacts are formed through the silicon oxide. The silicon oxide is selectively etched back to expose the silicon nitride slab. A portion or all the silicon nitride slab is removed and replaced with low-K dielectric or any dielectric with an air-gap to enable higher switching speed of the transistor. The highly-selective silicon nitride etch uses remotely excited fluorine and a very low electron temperature in the substrate processing region.

Protective silicon oxide patterning

Abstract: A method of patterning a substrate is described and include two possible layers which may be easily integrated into a photoresist patterning process flow and avoid an observed photoresist peeling problems. A conformal carbon layer or a conformal silicon-carbon-nitrogen layer may be formed between an underlying silicon oxide layer and an overlying photoresist layer. Either inserted layer may avoid remotely-excited fluorine etchants from diffusing through the photoresist and chemically degrading the silicon oxide. The conformal carbon layer may be removed at the same time as the photoresist and the conformal silicon-carbon-nitrogen layer may be removed at the same time as the silicon oxide, limiting process complexity.

Critical Role of Silicon Nanoparticles Surface on Lithium Cell Electrochemical Performance Analyzed by FTIR, Raman, EELS, XPS, NMR, and BDS Spectroscopies

Abstract: A pluri-disciplinary approach and a combination of techniques are used here to finely describe the surface of silicon nanoparticles used as active material in negative composite electrodes for lithium batteries. Although the surface of silicon particles is playing a major role in the electrochemical performance, it has rarely been characterized in depth. With respect to infrared analysis, we propose an analytical protocol, derived from the studies devoted to high specific area silica samples. Three different nanometric silicon powders are studied: a commercial one and two home synthesized silicon powders with specially designed surfaces. With respect to previous works and common belief, we demonstrate, on the electrochemical performance, a favorable effect of a particular thin layer silicon oxide with a well-defined SiO2 composition at the extreme surface of the silicon particles.

Aluminum oxide selective etch

Abstract: Methods of selectively etching aluminum oxide from the surface of a patterned substrate are described. The etch selectively removes aluminum oxide relative to other metal oxides and silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium and/or silicon nitride. The methods include exposing aluminum oxide to plasma effluents formed in a remote plasma from a chlorine-containing precursor and a hydrocarbon. A remote plasma is used to excite the precursors and a local plasma is used to further excite the plasma effluents and accelerate ions toward the patterned substrate.

Contact clean in high-aspect ratio structures

Abstract: Method and apparatus for cleaning a substrate having a plurality of high-aspect ratio openings are disclosed. A substrate can be provided in a plasma processing chamber, where the substrate includes the plurality of high-aspect ratio openings, the plurality of high-aspect ratio openings are defined by vertical structures having alternating layers of oxide and nitride or alternating layers of oxide and polysilicon. The substrate can include a silicon oxide layer over a damaged or amorphous silicon layer in the high-aspect ratio openings. To remove the silicon oxide layer, a bias power can be applied in the plasma processing chamber at a low pressure, and a fluorine-based species can be used to etch the silicon oxide layer. To remove the underlying damaged or amorphous silicon layer, a source power and a bias power can be applied in the plasma processing chamber, and a hydrogen-based species can be used to etch the damaged or amorphous silicon layer.

Silicon oxide selective removal

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than a second exposed portion. The inclusion of the oxygen-containing precursor may suppress the second exposed portion etch rate and result in unprecedented silicon oxide etch selectivity.

Aluminum oxide barrier coatings on polymer films for food packaging applications

Abstract: In the field of packaging, barrier layers are functional films, which can be applied to polymeric substrates with the objective of enhancing their end-use properties. For food packaging applications, the packaging material is required to preserve packaged food stuffs and protect them from a variety of environmental influences, particularly moisture and oxygen ingress and UV radiation. Aluminum metallized films are widely used for this purpose. More recently, transparent barrier coatings based on aluminum oxide or silicon oxide have been introduced in order to fulfill requirements such as product visibility, microwaveability or retortability. With the demand for transparent barrier films for low-cost packaging applications growing, the use of high-speed vacuum deposition techniques, such as roll-to-roll metallizers, has become a favorable and powerful tool. In this study, aluminum oxide barrier coatings have been deposited onto biaxially oriented polypropylene and polyethylene terephthalate film substrates via reactive evaporation using an industrial 'boat-type' roll-to-roll metallizer. The coated films have been investigated and compared to uncoated films in terms of barrier properties, surface topography, roughness and surface energy using scanning electron microscopy, atomic force microscopy and contact angle measurement. Coating to substrate adhesion and coating thickness have been examined via peel tests and transmission electron microscopy, respectively. © 2013 Elsevier B.V.

Effect of Reaction Mechanism on Precursor Exposure Time in Atomic Layer Deposition of Silicon Oxide and Silicon Nitride

Abstract: Atomic layer deposition (ALD) of highly conformal, silicon-based dielectric thin films has become necessary because of the continuing decrease in feature size in microelectronic devices. The ALD of oxides and nitrides is usually thought to be mechanistically similar, but plasma-enhanced ALD of silicon nitride is found to be problematic, while that of silicon oxide is straightforward. To find why, the ALD of silicon nitride and silicon oxide dielectric films was studied by applying ab initio methods to theoretical models for proposed surface reaction mechanisms. The thermodynamic energies for the elimination of functional groups from different silicon precursors reacting with simple model molecules were calculated using density functional theory (DFT), explaining the lower reactivity of precursors toward the deposition of silicon nitride relative to silicon oxide seen in experiments, but not explaining the trends between precursors. Using more realistic cluster models of amine and hydroxyl covered surfaces, the structures and energies were calculated of reaction pathways for chemisorption of different silicon precursors via functional group elimination, with more success. DFT calculations identified the initial physisorption step as crucial toward deposition and this step was thus used to predict the ALD reactivity of a range of amino-silane precursors, yielding good agreement with experiment. The retention of hydrogen within silicon nitride films but not in silicon oxide observed in FTIR spectra was accounted for by the theoretical calculations and helped verify the application of the model.

Low-k dielectric gapfill by flowable deposition

Abstract: Methods are described for forming a flowable low-k dielectric layer on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. A similarly deposited silicon oxide layer may be deposited first to improve the gapfill capabilities. Alternatively, or in combination, the flow of a silicon-and-carbon-containing precursor may be reduced during deposition to change the properties from low-k to high strength roughly following the filling of features of the patterned substrate.

Phosphorus doping of Si nanocrystals embedded in silicon oxynitride determined by atom probe tomography

Abstract: Silicon nanocrystals (SiNCs) embedded in a silicon oxide matrix were studied by 3D atom probe tomography (APT). The distribution of the SiNC diameter was found to have a mean value of 3.7 ± 0.8 nm. The elemental composition of these particles was determined by employing two different approaches: (i) The proximity histogram method and (ii) a cluster identification algorithm based on maximum-atom separations. Both approaches give very similar values in terms of the amount of P, O, and Si within the SiNCs: the mean atomic concentrations are cP = 0.77% ± 0.4%, cO = 12.3% ± 2.1%, and cSi = 85.3% ± 2.1%. A detailed cluster analysis implies that, on average, a 4.5-nm SiNC would contain around 30 P atoms, whereas a 2.0-nm SiNC would contain only around 3 P atoms. Radial concentration profiles obtained for these SiNCs indicate that the P content is inhomogeneous and possibly enhanced at the boundary as compared to the interior of the NCs. About 20% of the P atoms are found to be incorporated into the SiNCs, whereas roughly 30% are trapped within the interfacial layer (with a thickness of ∼ 0.8 nm); the remainder resides in the surrounding matrix. Cluster-size dependent P concentrations support the view of self-purification in the Si nanostructures.

van der Waals screening by single-layer graphene and molybdenum disulfide.

Abstract: A sharp tip of atomic force microscope is employed to probe van der Waals forces of a silicon oxide substrate with adhered graphene. Experimental results obtained in the range of distances from 3 to 20 nm indicate that single-, double-, and triple-layer graphenes screen the van der Waals forces of the substrate. Fluorination of graphene, which makes it electrically insulating, lifts the screening in the single-layer graphene. The van der Waals force from graphene determined per layer decreases with the number of layers. In addition, increased hole doping of graphene increases the force. Finally, we also demonstrate screening of the van der Waals forces of the silicon oxide substrate by single- and double-layer molybdenum disulfide.

Doped silicon oxide etch

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove two separate regions of silicon oxide at distinct etch rates. The methods may be used to remove doped silicon oxide faster than undoped silicon oxide or more lightly-doped silicon oxide. The relative humidity in the substrate processing region may be low during the etch process to increase the etch selectivity of the doped silicon oxide.