Silicon oxide

About: Silicon oxide is a research topic. Over the lifetime, 22220 publications have been published within this topic receiving 260986 citations.

Charge trapping properties at silicon nitride/silicon oxide interface studied by variable-temperature electrostatic force microscopy

Abstract: Charge trapping properties of electrons and holes in ultrathin nitride-oxide-silicon (NOS) structures were quantitatively determined by variable-temperature electrostatic force microscopy (EFM). From charge retention characteristics obtained at temperatures between 250 and 370°C and assuming that the dominant charge decay mechanism is thermal emission followed by oxide tunneling, we find that there are considerable deep trap centers at the nitride-oxide interface. For electron, the interface trap energy and density were determined to be about 1.52eV and 1.46×1012cm−2, respectively. For hole, these are about 1.01eV and 1.08×1012cm−2, respectively. In addition, the capture cross section of electron can be extracted to be 4.8×10−16cm2. The qualitative and quantitative determination of charge trapping properties and possible charge decay mechanism reported in this work can be very useful for the characterization of oxide-nitride-silicon based charge storage devices.

Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits

Abstract: A method is achieved for making improved shallow trench isolation (STI) regions surrounding and electrically isolating device areas on a substrate using dielectric studs, spin-on-glass (SOG), and an isotropic wet etchback The method consists of forming trenches in a silicon substrate using a pad oxide and silicon nitride mask A thermal oxide is grown in the silicon trenches and a CVD silicon oxide is deposited and chemical/mechanically polished back to the silicon nitride masking layer to form dielectric studs (or plugs) in the silicon trenches that extend above the silicon substrate surface The silicon nitride is removed in hot phosphoric acid, and a thin SOG is deposited to form disposable sidewall spacers on the raised studs The thin SOG and the pad oxide are wet etched in HF acid to the device areas while isotropically etching back the disposable SOG sidewall spacers and dielectric studs to form shallow trench isolation regions having a raised convex surface This eliminates dishing in the STI (concave STI) that results in undesirable variation in FET threshold voltage (Vth) The gradual convex profile also minimizes the polysilicon residue problem when anisotropically etching the gate electrodes over the device areas The use of SOG with wet etchback is more cost effective than the conventional CVD oxide deposition and plasma etchback process

Method of forming mask pattern and method of manufacturing semiconductor device

Abstract: A method of forming a mask pattern includes a first pattern forming step of etching an anti-reflection coating film by using as a mask a first line portion made up of a photo resist film formed on the anti-reflection film to form a pattern including a second line portion made up of the photo resist film and the anti-reflection film; an irradiation step of irradiating the photo resist film with electrons; a silicon oxide film forming step to cover the second line portion isotropically; and an etch back step of etching back the silicon oxide film such that the silicon oxide film is removed from the top of the second line portion as sidewalls of the second line portion. The method further includes a second pattern forming step of ashing the second line portion to form a mask pattern including a third line portion made up of the silicon oxide film and remains.

Swelling of a Polyelectrolyte Brush in Humid Air

Abstract: We present an experimental study on the swelling of polyelectrolyte brushes covalently attached to planar solid surfaces in contact with humid air. Monolayers of poly-N-methyl-[4-vinylpyridinium]iodide (MePVP) with film thicknesses of several hundred nanometers were used in this study. The MePVP brushes were attached to the surfaces of silicon wafers as well as to evaporated silicon oxide films on solid substrates by using self-assembled monolayers of an azo initiator and radical chain polymerization in situ. The film thicknesses of the surface-bound monolayers were measured by optical waveguide spectroscopy (OWS) as a function of the humidity of the environment. The MePVP brushes show strong increases in thickness as well as a strong decrease of the refractive index of the surface-attached layer due to water incorporation caused by the exposure to the humid environment.

Silicon selective removal

Abstract: A method of etching exposed silicon on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma The remote plasma excites a fluorine-containing precursor Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a hydrogen-containing precursor The combination react with the patterned heterogeneous structures to remove an exposed silicon portion faster than a second exposed portion The silicon selectivity results from the presence of an ion suppressor positioned between the remote plasma and the substrate processing region The methods may be used to selectively remove silicon faster than silicon oxide, silicon nitride and a variety of metal-containing materials The methods may be used to remove small etch amounts in a controlled manner and may result in an extremely smooth silicon surface