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Silicon oxide

About: Silicon oxide is a research topic. Over the lifetime, 22220 publications have been published within this topic receiving 260986 citations.


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Patent
Shizuo Oguro1
29 Sep 1992
TL;DR: In this article, a method of forming a polycrystalline silicon film on a silicon oxide film is described, in which the poly-crystallines silicon film includes crystal grains having a large size, typically 4 micrometers, thereby permitting the resistivity of the poly crystal silicon film to effectively be reduced.
Abstract: Disclosed is a method of forming a polycrystalline silicon film on a silicon oxide film in which the polycrystalline silicon film includes crystal grains having a large size, typically 4 micrometers, thereby permitting the resistivity of the polycrystalline silicon film to effectively be reduced. An amorphous silicon film is deposited on the silicon oxide film by using a chemical vapor deposition in which the flow rate of impurity gas remains at zero during an initial deposition, after which the flow rate is gradually increased from zero to a predetermined value during a final deposition. Thus, the amorphous silicon film comprises double layers, or an impurity unmixed region abutting the silicon oxide film and an impurity mixed region. After that, by a heat treatment, the amorphous silicon film is crystallized to form a polycrystalline silicon film. Concurrently, the impurity diffusion is accomplished.

76 citations

Journal ArticleDOI
TL;DR: In this article, a wet oxidation in steam ambience is applied and experimentally compared to a standard dry oxidation to improve the cost-effectiveness of the oxidation process, and 19.3% efficiency is obtained as best value on 4cm 2 cell area.
Abstract: Thermal oxides are commonly used for the surface passivation of high-efficiency silicon solar cells from mono- and multicrystalline silicon and have led to the highest conversion efficiencies reported so far. In order to improve the cost-effectiveness of the oxidation process, a wet oxidation in steam ambience is applied and experimentally compared to a standard dry oxidation. The processes yield identical physical properties of the oxide. The front contact is created using a screen-printing process of a hotmelt silver paste in combination with light-induced silver plating. The contact formation on the front requires a short high-temperature firing process, therefore the thermal stability of the rear surface passivation is very important. The surface recombination velocity of the fired oxide is experimentally determined to be below S ≤ 38 cm/s after annealing with a thin layer of evaporated aluminium on top. Monocrystalline solar cells are produced and 19.3% efficiency is obtained as best value on 4cm 2 cell area. Simulations show the potential of the developed process to approach 20% efficiency.

75 citations

Patent
23 Jan 1991
TL;DR: In this paper, a high pressure, high throughput, single wafer, semiconductor processing reactor is described which is capable of thermal CVD, plasma-enhanced CVD and plasma assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

75 citations

Patent
28 Jan 2000
TL;DR: In this article, the problem of adjusting input/output capacitance of a semiconductor device meeting the maximum and minimum standards or a customer's request is solved by changing the pattern of the metal switch section BP2 of the bonding pad BP.
Abstract: PROBLEM TO BE SOLVED: To adjust input/output capacitance of a semiconductor device meeting the maximum and minimum standards or a customer's request. SOLUTION: On the main surface of a semiconductor substrate 1, a thick silicon oxide film 2 which functions as an element isolation region is formed and a first electrode 6 is formed on the silicon oxide film 6 in a peripheral circuit region. The first electrode 6 is formed simultaneously with a gate electrode 4 of a MISFET Qs for memory cell selection. In addition, the first electrode 4, the substrate 1 which is a second electrode, and silicon oxide film 2 held between the electrode 6 and substrate 1 constitute a parallel plate capacitance element CA. Moreover, the first electrode 6 is connected electrically connected to a bonding pad BP of a third-layer wiring M3. The selection whether or not the electrode 6 is connected to the bonding section BP1 of the bonding pad BP is performed, by changing the pattern of the metal switch section BP2 of the bonding pad BP.

75 citations

Patent
18 May 1995
TL;DR: In this paper, a magnetic recording medium has a structure in which an undercoating film, a magnetic thin layer, a protective layer, and an organic layer are stacked on a substrate in the order named.
Abstract: This invention relates to a magnetic recording medium having a structure in which an undercoating film, a magnetic thin film, a protective film, and an organic film are stacked on a substrate in the order named. Since the protective film contains carbon and silicon and a portion of silicon in at least an interface in contact with the organic film consists of a silicon oxide, the surface of the magnetic recording medium is not degraded even by frequent contact with a magnetic head upon driving or stopping of the magnetic recording medium. This invention also relates to a method of manufacturing the same.

75 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202323
202253
2021199
2020524
2019649
2018621