Topic
Silicon oxide
About: Silicon oxide is a research topic. Over the lifetime, 22220 publications have been published within this topic receiving 260986 citations.
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Patent•
TDK1
TL;DR: A thermistor material comprising, in sintered form, a matrix comprising aluminum oxide, silicon oxide, or the oxide of an element belonging to Group 2A in the Periodic Table, and a conductive path forming substance comprising silicon carbide and/or boron carbide, wherein the volume ratio of silicon carbides to the matrix is up to about 1.24 is stable at elevated temperatures of 400°-800° C as discussed by the authors.
Abstract: A thermistor material comprising, in sintered form, (A) a matrix comprising aluminum oxide, silicon oxide, or the oxide of an element belonging to Group 2A in the Periodic Table, and (B) a conductive path forming substance comprising silicon carbide and/or boron carbide, wherein the volume ratio of silicon carbide to the matrix is up to about 1.24 is stable at elevated temperatures of 400°-800° C.
67 citations
Patent•
01 Jun 2006
TL;DR: In this paper, the problem of forming the memory cell of a split-gate nonvolatile semiconductor memory device was solved by forming a gate oxide film on both the side faces of the control gate electrode.
Abstract: PROBLEM TO BE SOLVED: To surely form the memory cell of a split-gate nonvolatile semiconductor memory device, and to prevent the operation characteristics of an MOS transistor from being affected by the memory cell when forming the memory cell on the same semiconductor wafer as the MOS transistor. SOLUTION: A control gate electrode 13 composed of a polycrystal silicon is formed on a semiconductor wafer 11 composed of a silicon through a gate oxide film 12. On both the side faces of the control gate electrode 13, the laminate of silicon oxide film and silicon nitride film is deposited for the film thickness of about 7 nm, and a protecting and insulating film 14 is formed for protecting the control gate electrode 13 when forming a floating gate electrode 15. On one side face of the control gate electrode 13, the floating gate electrode 15 of capacitive coupling with the control gate electrode 13 is formed while facing the control gate electrode through the protecting and insulating film 14. COPYRIGHT: (C)2006,JPO&NCIPI
67 citations
Patent•
17 Apr 1995TL;DR: In this paper, a gate electrode is formed through a gate insulating film on a channel region between the source and drain layers to induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer.
Abstract: A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.
67 citations
Patent•
NEC1
TL;DR: In this article, a manufacturing method of a semiconductor integrated circuit utilizing a trench isolated region to control the occurrence of parasitic transistors without narrowing the element region by forming first and second openings 4A, 4B on a silicon substrate for the purpose of element isolation, forming an amorphous silicon film thereon, then leaving the amorphus film behind only a surface of a side wall of the opening by performing anisotropy etching.
Abstract: A manufacturing method of a semiconductor integrated circuit utilizing a trench isolated region to control the occurrence of parasitic transistors without narrowing the element region by forming first and second openings 4A, 4B on a silicon substrate for the purpose of element isolation, forming an amorphous silicon film thereon, then leaving the amorphous silicon film behind only a surface of a side wall of the opening by performing anisotropy etching. After oxidizing the surface of the amorphous silicon film and inside base, the opening is filled with a silicon oxide film.
67 citations
Patent•
24 Apr 2015TL;DR: In this article, a method of removing amorphous silicon/silicon oxide film stack from vias is described, which is particularly well suited for 3D NAND (e.g. VNAND) device formation.
Abstract: A method of removing an amorphous silicon/silicon oxide film stack from vias is described. The method may involve a remote plasma comprising fluorine and a local plasma comprising fluorine and a nitrogen-and-hydrogen-containing precursor unexcited in the remote plasma to remove the silicon oxide. The method may then involve a local plasma of inert species to potentially remove any thin carbon layer (leftover from the photoresist) and to treat the amorphous silicon layer in preparation for removal. The method may then involve removal of the treated amorphous silicon layer with several options possibly within the same substrate processing region. The bottom of the vias may then possess exposed single crystal silicon which is conducive to epitaxial single crystal silicon film growth. The methods presented herein may be particularly well suited for 3d NAND (e.g. VNAND) device formation.
67 citations