Topic
Silicon oxide
About: Silicon oxide is a research topic. Over the lifetime, 22220 publications have been published within this topic receiving 260986 citations.
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15 Nov 1984TL;DR: In this paper, the interlayers of said clay have been intercalated with three-dimensional silicon oxide pillars whereby the pillars comprise at least two silicon atom layers parallel to the clay interlayer.
Abstract: The present invention relates to intercalated clay compositions wherein the interlayers of said clay have been intercalated with three-dimensional silicon oxide pillars whereby the pillars comprise at least two silicon atom layers parallel to the clay interlayers. These materials have useful catalytic and adsorbent properties.
59 citations
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TL;DR: In this paper, a low-emissivity (low-E) coatings with an oxide/silver/oxide/glass system was investigated, and the structure information, surface morphology and palladium concentration of the coatings were obtained from X-ray diffraction analysis (XRD), scanning electron microscopy (SEM) and inductive-coupled plasma spectroscopy (ICP), respectively.
59 citations
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59 citations
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28 Jun 2000TL;DR: In this article, a dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoressist mask.
Abstract: A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask. The improved process of the invention comprises: forming a first hard mask layer over an upper layer of low k carbon-doped silicon oxide dielectric material previously formed over an etch stop layer formed over a lower layer of low k carbon-doped silicon oxide dielectric material on an integrated circuit structure; forming a first photoresist mask having a pattern of via openings therein over the first hard mask layer; etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first hard mask; then removing the first photoresist mask; forming a second hard mask layer over the first hard mask; forming a second photoresist mask having a pattern of trench openings therein over the second hard mask layer; etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first and second hard masks; then removing the second photoresist mask; then using the first and second hard masks to respectively form the via openings in the lower layer of low k carbon-doped silicon oxide dielectric material and trench openings in the upper layer of low k carbon-doped silicon oxide dielectric material; whereby a pattern of via openings and a pattern of trench openings can be formed in layers of low k carbon-doped silicon oxide dielectric material without damage to the low k carbon-doped silicon oxide dielectric material during removal of the photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings.
59 citations
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12 Aug 1999TL;DR: In this article, a process for creating a dual damascene opening in a composite insulator layer, to be used to accommodate a dual-damascene copper structure, has been developed.
Abstract: A process for creating a dual damascene opening, in a composite insulator layer, to be used to accommodate a dual damascene copper structure, has been developed. The process features the use of a composite insulator layer, comprised with silicon oxide layers, and with multiple silicon nitride layers, used as stop layers, during selective, anisotropic RIE procedures, used to create the dual damascene opening, in the composite insulator layer. The multiple silicon nitride stop layers, are maintained at minimum thicknesses, to still allow selective formation of the dual damascene opening, however avoiding the capacitance increases, encountered with thicker silicon nitride counterparts. A dual damascene copper structure, formed in the dual damascene opening, exhibits minimum RC delays, as a result of the use of low resistivity copper, and as a result of the use of a minimum of silicon nitride etch stop layers, in the composite insulator.
59 citations