scispace - formally typeset
Search or ask a question
Topic

Silicon oxide

About: Silicon oxide is a research topic. Over the lifetime, 22220 publications have been published within this topic receiving 260986 citations.


Papers
More filters
Patent
Syun-Ming Jang1, Chen-Hua Yu1
16 Nov 1995
TL;DR: In this paper, a gap filling and self-planarizing silicon oxide insulator spacer layer within a patterned integrated circuit (PIIC) layer is proposed to fill the gap in the IC.
Abstract: A method for forming a gap-filling and self-planarizing silicon oxide insulator spacer layer within a patterned integrated circuit layer. Formed upon a semiconductor substrate is a patterned integrated circuit layer which is structured with a titanium nitride upper-most layer. The patterned integrated circuit layer also has at least one lower-lying layer formed of a material having a growth rate with respect to ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers greater than the growth rate of ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers upon titanium nitride. Formed within and upon the patterned integrated circuit layer is a silicon oxide insulator spacer layer deposited through an ozone assisted Chemical Vapor Deposition (CVD) process. The silicon oxide insulator spacer layer is formed until the surface of the titanium nitride upper-most layer is passivated with the silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is then etched from the surface of the titanium nitride upper-most layer. Finally, additional portions of the silicon oxide insulator spacer layer are sequentially deposited and etched until the surface of the silicon oxide insulator spacer layer over the lower layer(s) of the patterned integrated circuit layer is planar with the upper surface of the titanium nitride upper-most layer of the patterned integrated circuit layer.

203 citations

Patent
10 Jul 2006
TL;DR: In this paper, a batch of wafer substrates is provided with each wafer substrate having a surface and each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of WF substrates.
Abstract: A batch of wafer substrates is provided with each wafer substrate having a surface. Each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of wafer substrates. The layer of material is applied to a thickness that varies less than four thickness percent across the surface and exclusive of an edge boundary and having a wafer-to-wafer thickness variation of less than three percent. The layer of material so applied is a silicon oxide, silicon nitride or silicon oxynitride with the layer of material being devoid of carbon and chlorine. Formation of silicon oxide or a silicon oxynitride requires the inclusion of a co-reactant. Silicon nitride is also formed with the inclusion of a nitrification co-reactant. A process for forming such a batch of wafer substrates involves feeding the precursor into a reactor containing a batch of wafer substrates and reacting the precursor at a wafer substrate temperature, total pressure, and precursor flow rate sufficient to create such a layer of material. The delivery of a precursor and co-reactant as needed through vertical tube injectors having multiple orifices with at least one orifice in registry with each of the batch of wafer substrates and exit slits within the reactor to create flow across the surface of each of the wafer substrates in the batch provides the within- wafer and wafer-to-wafer uniformity.

201 citations

Patent
07 May 2009
TL;DR: In this paper, a method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectrics etch rate in fluorine-containing etch chemistries.
Abstract: A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.

201 citations

Patent
19 Feb 2014
TL;DR: In this article, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursors and the precursor adsorb on the substrate surface.
Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.

199 citations

Patent
14 Nov 1988
TL;DR: In this article, a back surface point contact silicon solar cell having improved characteristics is fabricated by hydrogenating a silicon-silicon oxide interface where hydrogen atoms are diffused through silicon nitride and silicon oxide passivating layers on the surface of a silicon substrate.
Abstract: A back surface point contact silicon solar cell having improved characteristics is fabricated by hydrogenating a silicon-silicon oxide interface where hydrogen atoms are diffused through silicon nitride and silicon oxide passivating layers on the surface of a silicon substrate. In carrying out the hydrogenation, the substrate and passivation layers are placed in a hydrogen atomsphere at an elevated temperature of at least 900° C. whereby hydrogen atoms diffuse through the two passivation layers. Self-alignment techniques are employed in forming small-geometry doped regions in the surface of the silicon substrate for the p-n junctions of the solar cell. Openings are formed through the passivation layers to expose first surface areas on the substrate, and a doped silicon oxide layer is then formed over the passivation layers and on the exposed surface areas. Portions of the first doped layer on the two passivation layers are removed and then second portions of the two passivation layers are removed, thereby exposing second surface areas. A second doped silicon oxide layer is then formed over the passivation layers and on the second exposed surface areas. Dopants from the two doped silicon oxide layers are then diffused into the first and second surface layers to form p and n diffused regions in the surface of the substrate. Thereafter, the first and second doped silicon oxide layers are removed by a preferential etchant which does not remove the silicon nitride layer, thereby exposing the first and second surface areas. A two-level metal interconnect structure is then formed for separately contacting the first surface areas and the second surface areas.

195 citations


Network Information
Related Topics (5)
Thin film
275.5K papers, 4.5M citations
96% related
Silicon
196K papers, 3M citations
94% related
Band gap
86.8K papers, 2.2M citations
93% related
Amorphous solid
117K papers, 2.2M citations
92% related
Oxide
213.4K papers, 3.6M citations
91% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202323
202253
2021199
2020524
2019649
2018621