Silicon oxide

About: Silicon oxide is a research topic. Over the lifetime, 22220 publications have been published within this topic receiving 260986 citations.

3D Silicon oxide nanostructures: from nanoflowers to radiolaria

Abstract: Novel flower-like nanostructures consisting of silicon oxide nanofibers, radially attached to a single catalytic particle, were generated by solid-solid and gas-solid reactions under a temperature gradient. In this process, a mixture of SiC and Co powders, deposited on silica substrates and heated under an Ar/CO atmosphere at ca. 1500C, produced material with unusual three-dimensional (3D) networks of nanofibers of uniform diameter (ca. 20-120nm) and length (ca. 10-250mu;m). Scanning electron microscopy (SEM), high resolution transmission electron microscopy (HRTEM), X-ray powder diffraction and energy dispersive X-ray (EDX) analyses reveal that the nanofibres are amorphous and consist only of silicon oxide, generated from the reaction of CO with SiC. Nanostructure formation is catalyzed by Co particles, which act as nucleation sites and templates for 3D growth. Experiments using Si3N4 and Si in conjunction with other catalysts (e.g. Fe, Ni and CoO) yield similar results and confirm that the resulting SiOx fibres display virtually unique and remarkable radial growth starting from single metal particles. These structures exhibit morphologies comparable to radiolarian and diatom skeletons and may provide insight into the formation of microbiological systems.

Semiconductor device and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To enable a resistor composed of a thin metallic film to obtain a stable resistance value by preventing the oxidation of the surface of the metallic film even when oxygen ashing is performed on a resist SOLUTION: A method of manufacturing a semiconductor device includes a step (a) of forming a thin metallic film 5 on a base insulating film 3; a step (b) of laminating a silicon nitride film 7 and a silicon oxide film 9 upon the film 5 in this order; and a step (c) of removing a photoresist pattern 11 by performing ashing by using oxygen plasma, after the pattern 11 is formed on the silicon oxide film 9 for demarcating a resistor forming area and a silicon oxide film pattern 9a is formed by selectively removing the silicon oxide film 9 by using the photoresist pattern 11 as a mask The method also includes a step (d) of forming a silicon nitride film pattern 7a by selectively removing the silicon nitride film 7 and thin metallic film 5 by using the silicon oxide film pattern 9a as a mask and forming a thin metallic film pattern 5a which becomes the resistor, and a step (e) of forming a oxidation preventing second silicon nitride film 13 on the side face of the thin metallic film pattern 5a COPYRIGHT: (C)2005,JPO&NCIPI

A silicon-thermopile-based infrared sensing array for use in automated manufacturing

Abstract: This paper describes a new low-cost infrared detector array that has been realized using standard silicon MOS process technology and micromachining. This array uses thermopiles as infrared detecting elements and multiple layers of silicon oxide and silicon nitride for diaphragm windows measuring 0.4 mm × 0.7 mm × 1.3 µm. Each thermopile consists of 40 polysilicon-gold thermocouples. A high fill factor for this array structure has been achieved by using the boron etch-stop technique to provide 20-µm thick silicon support rims. The array shows a response time of less than 10 ms, a responsivity of 12 V/ W; and a broad-band input spectral sensitivity. The process is compatible with silicon MOS devices, and a 16 × 2 staggered array with on-chip multiplexers has been designed for applications in process monitoring. The array theoretically achieves an NETD of 0.9°C and an MRTD of 1.4°C at a spatial frequency of 0.2 Hz/mrad in a typical imaging system.

Feol low-k spacers

Abstract: Transistors and their methods of formation are described. Low dielectric constant material (e.g. a void) is placed between an elongated gate and a contact to increase the attainable switching speed of the gate of the device. An elongated structural slab of silicon nitride is temporarily positioned on both sides of the gate. Silicon oxide is formed over the silicon nitride slabs and the gate. Contacts are formed through the silicon oxide. The silicon oxide is selectively etched back to expose the silicon nitride slab. A portion or all the silicon nitride slab is removed and replaced with low-K dielectric or any dielectric with an air-gap to enable higher switching speed of the transistor. The highly-selective silicon nitride etch uses remotely excited fluorine and a very low electron temperature in the substrate processing region.

Are electrical properties of an aluminum-porous silicon junction governed by dangling bonds?

Abstract: Using an aluminum–porous p+ silicon junction, we have realized a sensor which dc current increases up to two orders of magnitude in the presence of ammonia, as for a series of various gases. To interpret quantitatively this phenomenon, we assume that the conductivity is governed by the width of a channel resulting from the partial depletion of silicon located between two pores. This depleted region is due to the charges trapped on surface states associated with the Si–SiO2 interface where SiO2 is the native silicon oxide. When some gas is adsorbed, mainly on Si–H bonds, we propose there is an electrical screening of the interface states (mainly dangling bonds located in the neighborhood of the Si–H bonds), leading to a decrease of the depleted region, i.e., an increase of the width of the channel and thus an increase of the current.