Single event upset

About: Single event upset is a research topic. Over the lifetime, 1993 publications have been published within this topic receiving 31949 citations.

Rate prediction for single event effects-a critique

Abstract: The authors review various single event effects (SEE) testing and rate prediction methodologies and recommend standard approaches. This discussion is limited to single event upset (SEU) rate prediction for direct-ionization-induced effects. The standard approach being recommended is based partially on a different way of viewing the results of SEU cross-section measurements. The measurements are not measuring a distribution of cross-sections. They are measuring a distribution of device sensitivities, due to differences of sensitive region critical charges and to differences of charge collection. The linear energy transfer (LET), at which 50% of the cell population upsets, corresponds to the charge deposition necessary to upset the median cell in the circuit array. The threshold LET corresponds to the most sensitive region being hit in its most sensitive location, and does not represent the entire array. The shape of the cross-section curve is described by an integral Weibull distribution. The upset rate for a device should then be calculated using the differential rate of each sensitive region, combined with an integral weighting given by the Weibull distribution that describes the measured cross-section curve. >

Evaluation of error detection schemes using fault injection by heavy-ion radiation

Abstract: Several concurrent error detection schemes suitable for a watch-dog processor were evaluated by fault injection. Soft errors were induced into a MC6809E microprocessor by heavy-ion radiation from a Californium-252 source. Recordings of error behavior were used to characterize the errors as well as to determine coverage and latency for the various error detection schemes. The error recordings were used as input to programs that simulate the error detection schemes. The schemes evaluated detected up to 79% of all errors within 85 bus cycles. Fifty-eight percent of the errors caused execution to diverge permanently from the correct program. The best schemes detected 99% of these errors. Eighteen percent of the errors affected only data, and the coverage of these errors was at most 38%. >

Single event upset in avionics

Abstract: Data from military/experimental flights and laboratory testing indicate that typical non-radiation-hardened 64 K and 256 K static random access memories (SRAMs) can experience a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere. It is suggested that error detection and correction circuitry be considered for all avionics designs containing large amounts of semiconductor memory. >

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Abstract: Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

Fault-Tolerance Techniques for SRAM-Based FPGAs

Abstract: DEDICATION CONTRIBUTING AUTHORS PREFACE 1 INTRODUCTION 2 RADIATION EFFECTS IN INTEGRATED CIRCUITS 21 RADIATION ENVIROMENT OVERVIEW 22 RADIATION EFFECTS IN INTEGRATED CIRCUITS 221 SEU Classification 23 PECULIAR EFFECTS IN SRAM-BASED FPGAS 3 SINGLE EVENT UPSET (SEU) MITIGATION TECHNIQUES 31 DESIGN-BASED TECHNIQUES 311 Detection Techniques 312 Mitigation Techniques 3121 Full Time and Hardware Redundancy 3122 Error Correction and Detection Codes 3123 Hardened Memory Cells 32 EXAMPLES OF SEU MITIGATION TECHNIQUES IN ASICS 33 EXAMPLES OF SEU MITIGATION TECHNIQUES IN FPGAS 331 Antifuse based FPGAs 332 SRAM-based FPGAs 3321 SEU Mitigation Solution in high-level description 3322 SEU Mitigation Solutions at the Architectural level 3323 Recovery technique 4 ARCHITECTURAL SEU MITIGATION TECHNIQUES 5 HIGH-LEVEL SEU MITIGATION TECHNIQUES 51 TRIPLE MODULAR REDUNDANCY TECHNIQUE FOR FPGAS 52 SCRUBBING 6 TRIPLE MODULAR REDUNDANCY (TMR) ROBUSTNESS 61 TEST DESIGN METHODOLOGY 62 FAULT INJECTION IN THE FPGA BITSTREAM 63 LOCATING THE UPSET IN THE DESIGN FLOORPLANNING 631 Bit column location in the matrix 632 Bit row location in the matrix 633 Bit location in the CLB 634 Bit Classification 64 FAULT INJECTION RESULTS 65 THE 'GOLDEN' CHIP APPROACH 7 DESIGNING AND TESTING A TMR MICRO-CONTROLLER 71 AREA AND PERFORMANCE RESULTS 72 TMR 8051 MICRO-CONTROLLER RADIATION GROUND TEST RESULTS 8 REDUCING TMR OVERHEADS: PART I 81 DUPLICATION WITH COMPARISON COMBINED WITH TIME REDUNDANCY 82 FAULT INJECTION IN THE VHDL DESCRIPTION 83 AREA AND PERFORMANCE RESULTS 9 REDUCING TMR OVERHEADS: PART II 91 DWC-CED TECHNIQUE IN ARITHMETIC-BASED CIRCUITS 911 Using CEDbased on hardware redundancy 912 Using CED based on time redundancy 913 Choosing the most appropriated CED block 9131 Multipliers 9132 Arithmetic and Logic Unit (ALU) 9133 Digital FIR Filter 914 Fault Coverage Results 914 Area and Performance Results 92 DESIGNING DWC-CED TECHNIQUE IN NON-ARITHMETIC-BASED CIRCUITS 10 FINAL REMARKS REFERENCES