Topic
Smart Cache
About: Smart Cache is a research topic. Over the lifetime, 7680 publications have been published within this topic receiving 180618 citations.
Papers published on a yearly basis
Papers
More filters
•
14 Apr 2003
TL;DR: In this article, the authors employ receiving an operational parameter characteristic of a storage device, and adapt a read cache pre-fetch depth based in part on the operational parameter, which can be used to generate an operational parameters and vary the read cache depth in response to the operational parameters.
Abstract: Exemplary systems, methods, and devices employ receiving an operational parameter characteristic of a storage device, and adapting a read cache pre-fetch depth based in part on the operational parameter. An exemplary device includes a read cache memory and a read cache pre-fetch adaptation module operable to generate an operational parameter and vary read cache pre-fetch depth in response to the operational parameter.
74 citations
••
TL;DR: Simulation results show that the proposed method outperforms the exiting counterparts with a higher hit ratio and lower delay of delivering video contents, and leveraging the backward induction method, the optimal strategy of each player in the game model is proposed.
Abstract: To improve the performance of mobile video delivery, caching layered videos at a site near to mobile end users (e.g., at the edge of mobile service provider's backbone) was advocated because cached videos can be delivered to mobile users with a high quality of experience, e.g., a short latency. How to optimally cache layered videos based on caching price, the available capacity of cache nodes, and the social features of mobile users, however, is still a challenging issue. In this paper, we propose a novel edge caching scheme to cache layered videos. First, a framework to cache layered videos is presented in which a cache node stores layered videos for multiple social groups, formed by mobile users based on their requests. Due to the limited capacity of the cache node, these social groups compete with each other for the number of layers they request to cache, aiming at maximizing their utilities while all mobile users in each group share the cost involved in the cache of video contents. Second, a Stackelberg game model is developed to study the interaction among multiple social groups and the cache node, and a noncooperative game model is introduced to analyze the competition among mobile users in different social groups. Third, leveraging the backward induction method, the optimal strategy of each player in the game model is proposed. Finally, simulation results show that the proposed method outperforms the exiting counterparts with a higher hit ratio and lower delay of delivering video contents.
74 citations
•
20 Sep 2002TL;DR: Cache sharing for a chip multiprocessor is discussed in this paper, where a control mechanism is provided to allow sharing between caches that are associated with individual processor cores, each having an associated cache.
Abstract: Cache sharing for a chip multiprocessor. In one embodiment, a disclosed apparatus includes multiple processor cores, each having an associated cache. A control mechanism is provided to allow sharing between caches that are associated with individual processor cores.
74 citations
••
01 Dec 2012TL;DR: Amoeba-Cache is proposed, a design that supports a variable number of cache blocks, each of a different granularity, that adapts to the appropriate granularity both for different data objects in an application as well as for different phases of access to the same data.
Abstract: The fixed geometries of current cache designs do not adapt to the working set requirements of modern applications, causing significant inefficiency. The short block lifetimes and moderate spatial locality exhibited by many applications result in only a few words in the block being touched prior to eviction. Unused words occupy between 17 -- 80% of a 64K L1 cache and between 1% -- 79% of a 1MB private LLC. This effectively shrinks the cache size, increases miss rate, and wastes on-chip bandwidth. Scaling limitations of wires mean that unused-word transfers comprise a large fraction (11%) of on-chip cache hierarchy energy consumption. We propose Amoeba-Cache, a design that supports a variable number of cache blocks, each of a different granularity. Amoeba-Cache employs a novel organization that completely eliminates the tag array, treating the storage array as uniform and morph able between tags and data. This enables the cache to harvest space from unused words in blocks for additional tag storage, thereby supporting a variable number of tags (and correspondingly, blocks). Amoeba-Cache adjusts individual cache line granularities according to the spatial locality in the application. It adapts to the appropriate granularity both for different data objects in an application as well as for different phases of access to the same data. Overall, compared to a fixed granularity cache, the Amoeba-Cache reduces miss rate on average (geometric mean) by 18% at the L1 level and by 18% at the L2 level and reduces L1 -- L2 miss bandwidth by ?46%. Correspondingly, Amoeba-Cache reduces on-chip memory hierarchy energy by as much as 36% (mcf) and improves performance by as much as 50% (art).
74 citations
••
03 Jan 1989TL;DR: A technique is proposed to prevent the return of infrequently used items to cache after they are bumped from it, which involves the use of hardware called a bypass-cache, which will determine whether each reference should be through the cache or should bypass the cache and reference main memory directly.
Abstract: A technique is proposed to prevent the return of infrequently used items to cache after they are bumped from it. Simulations have shown that the return of these items, called cache pollution, typically degrade cache-based system performance (average reference time) by 10% to 30%. The technique proposed involves the use of hardware called a bypass-cache, which, under program control, will determine whether each reference should be through the cache or should bypass the cache and reference main memory directly. Several inexpensive heuristics for the compiler to determine how to make each reference are given. It is shown that much of the performance loss can be regained. >
74 citations