Smart Cache

About: Smart Cache is a research topic. Over the lifetime, 7680 publications have been published within this topic receiving 180618 citations.

CacheOptimizer: helping developers configure caching frameworks for hibernate-based database-centric web applications

Abstract: To help improve the performance of database-centric cloud-based web applications, developers usually use caching frameworks to speed up database accesses. Such caching frameworks require extensive knowledge of the application to operate effectively. However, all too often developers have limited knowledge about the intricate details of their own application. Hence, most developers find configuring caching frameworks a challenging and time-consuming task that requires extensive and scattered code changes. Furthermore, developers may also need to frequently change such configurations to accommodate the ever changing workload. In this paper, we propose CacheOptimizer, a lightweight approach that helps developers optimize the configuration of caching frameworks for web applications that are implemented using Hibernate. CacheOptimizer leverages readily-available web logs to create mappings between a workload and database accesses. Given the mappings, CacheOptimizer discovers the optimal cache configuration using coloured Petri nets, and automatically adds the appropriate cache configurations to the application. We evaluate CacheOptimizer on three open-source web applications. We find that i) CacheOptimizer improves the throughput by 27--138%; and ii) after considering both the memory cost and throughput improvement, CacheOptimizer still brings statistically significant gains (with mostly large effect sizes) in comparison to the application's default cache configuration and to blindly enabling all possible caches.

Two-level virtual/real set associative cache system and method with improved synonym detection

Abstract: A two-level virtual/real cache system, and a method for detecting and resolving synonyms in the two-level virtual/real cache system, are described. Lines of a first level virtual cache are tagged with a virtual address and a real pointer which points to a corresponding line in a second level real cache. Lines in the second level real cache are tagged with a real address and a virtual pointer which points to a corresponding line in the first level virtual cache, if one exists. A translation-lookaside buffer (TLB) is used for translating virtual to real addresses for accessing the second level real cache. Synonym detection is performed at the second level real cache. An inclusion bit I is set in a directory of the second level real cache to indicate that a particular line is included in the first level virtual cache. Another bit, called a buffer bit B, is set whenever a line in the first level virtual cache is placed in a first level virtual cache writeback buffer for updating main memory. When a first level cache miss occurs, the TLB generates a corresponding real address for that page and the first level virtual cache selects a line for replacement and also notifies the second level real cache which line it chooses for replacement. The real address is then used to access the second level real cache. Synonym detection and resolution are performed by the second level real cache.

Cache store clearing operation for multiprocessor mode

Abstract: In a multiprocessor data processing system, all processors must have access to certain communications tables stored in the main memory shared by the processors. Each processor has a cache store embedded within for its individual use. A cache store in one processor might contain data from the communication tables which is obsoleted by operations of a second processor. The cache store clearing apparatus invalidates its data information any time its processor accesses the communication tables. The cache store is cleared by resetting tag directory indicators, a round robin counter and a column full flag, for each column in a four level set associative tag directory to the cache store. The data in the cache store need not be cleared. Using the four level set associative tag directory permits the data information in the cache store to be invalidated by a 16 pulse burst of signals for 1K words of cache store directed to the tag directory indicators.

Microprocessor including a first level cache and a second level cache having different cache line sizes

Abstract: A microprocessor (100) including a first level cache (101) and a second level cache (130) having different cache line sizes. The microprocessor (100) includes an execution unit (124) configured to execute instructions and a cache subsystem coupled to the execution unit. The cache subsystem includes a first cache memory (101) configured to store a first plurality of cache lines each having a first number of bytes of data. The cache subsystem also includes a second cache memory (130) coupled to the first cache memory (101) and configured to store a second plurality of cache lines each having a second number of bytes of data. Each of the second plurality of cache lines includes a respective plurality of sub-lines each having the first number of bytes of data.

Cache system and method for prefetching of data

Abstract: A cache system which includes prefetch pointer fields for identifying lines of memory to prefetch thereby minimizing the occurrence of cache misses. This cache structure and method for implementing the same takes advantage of the previous execution history of the processor and the locality of reference exhibited by the requested addresses. In particular, each cache line contains a prefetch pointer field which contains a pointer to a line in memory to be prefetched and placed in the cache. By prefetching specified lines of data with temporal locality to the lines of data containing the prefetch pointers the number of cache misses is minimized.