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Smart Cache

About: Smart Cache is a research topic. Over the lifetime, 7680 publications have been published within this topic receiving 180618 citations.


Papers
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Journal ArticleDOI
01 May 1990
TL;DR: A new lock-based cache scheme which incorporates synchronization into the cache coherency mechanism, and a new simulation model is developed embodying a widely accepted paradigm of parallel programming that outperforms existing cache protocols.
Abstract: Introducing private caches in bus-based shared memory multiprocessors leads to the cache consistency problem since there may be multiple copies of shared data. However, the ability to snoop on the bus coupled with the fast broadcast capability allows the design of special hardware support for synchronization. We present a new lock-based cache scheme which incorporates synchronization into the cache coherency mechanism. With this scheme high-level synchronization primitives as well as low-level ones can be implemented without excessive overhead. Cost functions for well-known synchronization methods are derived for invalidation schemes, write update schemes, and our lock-based scheme. To accurately predict the performance implications of the new scheme, a new simulation model is developed embodying a widely accepted paradigm of parallel programming. It is shown that our lock-based protocol outperforms existing cache protocols.

53 citations

Patent
20 Jun 1997
TL;DR: In this article, a cache architecture with a first level cache and a second level cache is described, where the second-level cache lines include an inclusion vector which indicates which portion of that line are stored in the first-layer cache.
Abstract: A cache architecture with a first level cache and a second level cache, with the second level cache lines including an inclusion vector which indicates which portion of that line are stored in the first level cache. In addition, an instruction/data bit in the inclusion vector indicates whether a portion of that line is in the instruction cache at all. Thus, when a snoop is done to the level two cache, additional snoops to the level one cache only need to be done for those lines which are indicated as present by the inclusion vector.

53 citations

Patent
01 Mar 1999
TL;DR: In this paper, a storage control circuit is positioned between the first and second level 1 caches and a level 2 cache and main memory, which is used to prevent repeated writes to the same data by multiple processors.
Abstract: A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level 1 cache, and the second processor accesses data using a second level 1 cache. A storage control circuit is positioned between the first and second level 1 caches and a level 2 cache and main memory. The level 2 cache maintains copies of data in main storage and further maintains an indication of those level 1 caches having copies of data and whether those copies have been modified. When a processor accesses data that is not resident in the connected level 1 cache, a request is delivered to the level 2 cache for this data. The level 2 cache then determines whether it can return a copy of the data to the level 1 cache or must access the data from main memory. Also, when the level 2 cache determines that another level 1 cache is storing a modified copy of the data, the level 2 cache returns to the storage control circuit a pointer to the level 1 cache having the modified copy of the data; the storage control circuit then causes the level 1 cache having a modified copy of the data, to transfer the modified data to the requesting level 1 cache without returning the data to the level 2 cache or main memory. This ameliorates the effects of repeated writes to the same data by the multiple processors.

53 citations

Patent
27 Jan 2010
TL;DR: In this paper, a processor may include several processor cores, each including a respective higher-level cache; a lower level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks.
Abstract: A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.

53 citations

Book ChapterDOI
TL;DR: An experimental comparison of cache aware and cache oblivious static search tree algorithms is presented and it is shown that cache aware algorithms with implicit pointers perform best overall, but cache oblivious algorithms do almost as well and do not have to be tuned to the memory block size as cacheaware algorithms require.
Abstract: An experimental comparison of cache aware and cache oblivious static search tree algorithms is presented. Both cache aware and cache oblivious algorithms outperform classic binary search on large data sets because of their better utilization of cache memory. Cache aware algorithms with implicit pointers perform best overall, but cache oblivious algorithms do almost as well and do not have to be tuned to the memory block size as cache aware algorithms require. Program instrumentation techniques are used to compare the cache misses and instruction counts for implementations of these algorithms.

53 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202350
2022114
20215
20201
20198
201818