Topic
Smart Cache
About: Smart Cache is a research topic. Over the lifetime, 7680 publications have been published within this topic receiving 180618 citations.
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Patent•
09 Apr 1998
TL;DR: In this paper, a request address buffer registers physical and virtual addresses associated with an instruction of a miss request by the processor to the L1 cache, with an ID that is sent to the first cache with the miss request.
Abstract: A processor prefetches instructions in a pipelined manner from a first (L1) cache to a local instruction cache, with an instruction pointer device being utilized to select one of a plurality of incoming addresses for fetching purposes. Instructions returned from the L1 cache are stored in an instruction streaming buffer before they are actually written into the instruction cache. A way multiplexer outputs instructions to dispersal logic in the processor, and is fed by either the local cache or a bypass path that provides the instruction to the way multiplexer from a plurality of bypass sources, which includes the instruction streaming buffer. A request address buffer registers physical and virtual addresses associated with an instruction of a miss request by the processor to the L1 cache. Each entry of the request address buffer has an ID that is sent to the L1 cache with the miss request. This ID is returned to the request address buffer from the L1 cache to read out into the streaming buffer the physical and virtual addresses corresponding to the instruction of the miss request.
47 citations
Patent•
25 Feb 2013TL;DR: In this article, the authors propose a method of enabling fast suspend and resume of virtual machines (VMs) employing a cache that is able to perform input/output operations at a faster rate than a storage device provisioned for the VMs.
Abstract: A method of enabling “fast” suspend and “rapid” resume of virtual machines (VMs) employs a cache that is able to perform input/output operations at a faster rate than a storage device provisioned for the VMs. The cache may be local to a computer system that is hosting the VMs or may be shared cache commonly accessible to VMs hosted by different computer systems. The method includes the steps of saving the state of the VM to a checkpoint file stored in the cache and locking the checkpoint file so that data blocks of the checkpoint file are maintained in the cache and are not evicted, and resuming execution of the VM by reading into memory the data blocks of the checkpoint file stored in the cache.
47 citations
Patent•
03 Jul 2012
TL;DR: In this article, a virtual machine cache provides for maintaining a working set of the cache during a transfer between virtual machine hosts, where a previous host retains cache data of the virtual machine, which is provided to the new host of the VM.
Abstract: A virtual machine cache provides for maintaining a working set of the cache during a transfer between virtual machine hosts. In response to the transfer, a previous host retains cache data of the virtual machine, which is provided to the new host of the virtual machine. The cache data may be transferred via a network transfer.
47 citations
TL;DR: A write intensity predictor that realizes the idea by exploiting a correlation between write intensity of blocks and memory access instructions that incur cache misses of those blocks is designed and a hybrid cache architecture in which write-intensive blocks identified by the predictor are placed into the SRAM region is designed.
Abstract: Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density alternative to SRAM for large on-chip caches. However, its high write energy has been considered as a serious drawback. Hybrid caches mitigate this problem by incorporating a small SRAM cache for write-intensive data along with an STT-RAM cache. In such architectures, choosing cache blocks to be placed into the SRAM cache is the key to their energy efficiency. This paper proposes a new hybrid cache architecture called prediction hybrid cache. The key idea is to predict write intensity of cache blocks at the time of cache misses and determine block placement based on the prediction. We design a write intensity predictor that realize the idea by exploiting a correlation between write intensity of blocks and memory access instructions that incur cache misses of those blocks. It includes a mechanism to dynamically adapt the predictor to application characteristics. We also design a hybrid cache architecture in which write-intensive blocks identified by the predictor are placed into the SRAM region. Evaluations show that our scheme reduces energy consumption of hybrid caches by 28 percent (31 percent) on average compared to the existing hybrid cache architecture in a single-core (quad-core) system.
47 citations
Patent•
17 Sep 2002
TL;DR: In this paper, a hybrid system for updating cache including a first computer system coupled to a database accessible by a second computer system, including a cache, a cache update controller for concurrently implementing a user defined cache update policy, including both notification based cache updates and periodic-based cache updates.
Abstract: A hybrid system for updating cache including a first computer system coupled to a database accessible by a second computer system, said second computer system including a cache, a cache update controller for concurrently implementing a user defined cache update policy, including both notification based cache updates and periodic based cache updates, wherein said cache updates enforce data coherency between said database and said cache, and a graphical user interface for selecting between said notification based cache updates and said periodic based cache updates.
47 citations