Smart Cache

About: Smart Cache is a research topic. Over the lifetime, 7680 publications have been published within this topic receiving 180618 citations.

Cache-efficient object loader

Abstract: An improved object loader is provided that is designed to take advantage of the caching architecture of many of today's processors to improve performance. Some of today's most advanced processors, like the PENTIUM processor, have a two-level caching scheme utilizing both a primary cache and a secondary cache, where data contained in the primary cache is accessible 50 to 150 times faster than data in main memory. The improved object loader uses a hash table and an object handle table to load objects, where each of these tables is designed and utilized in such a manner so as to take full advantage of the processor's caching architecture to increase system performance.

The Difference-Bit Cache

Abstract: The difference-bit cache is a two-way set-associative cache with an access time that is smaller than that of a conventional one and close or equal to that of a direct-mapped cache. This is achieved by noticing that the two tags for a set have to differ at least by one bit and by using this bit to select the way. In contrast with previous approaches that predict the way and have two types of hits (primary of one cycle and secondary of two to four cycles), all hits of the difference-bit cache are of one cycle. The evaluation of the access time of our cache organization has been performed using a recently proposed on-chip cache access model.

On the throughput capacity of information-centric networks

Abstract: Wireless information-centric networks consider storage one of the network primitives, and propose to cache data within the network in order to improve latency to access content and reduce bandwidth consumption. We study the throughput capacity of an information-centric network when the data cached in each node has a limited lifetime. The results show that with some fixed request and cache expiration rates, the network can have the maximum throughput order of 1/√n and 1/log n in cases of grid and random networks, respectively. Comparing these values with the corresponding throughput with no cache capability (1/n and 1/√(n log n) respectively), we can actually quantify the asymptotic advantage of caching. Moreover, since the request rates will decrease as a result of increasing download delays, increasing the content lifetimes according to the network growth may result in higher throughput capacities.

Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache

Abstract: A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

Non-volatile cache

Abstract: Apparatuses, systems, and methods are disclosed for caching data. A method includes directly mapping a logical address of a backing store to a logical address of a non-volatile cache. A method includes mapping, in a logical-to-physical mapping structure, the logical address of the non-volatile cache to a physical location in the non-volatile cache. The physical location may store data associated with the logical address of the backing store. A method includes removing the mapping from the logical-to-physical mapping structure in response to evicting the data from the non-volatile cache so that membership in the logical-to-physical mapping structure denotes storage in the non-volatile cache.