About: Snapback is a(n) research topic. Over the lifetime, 742 publication(s) have been published within this topic receiving 8225 citation(s).
Papers published on a yearly basis
Abstract: Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.
Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.
01 Jan 1996
Abstract: A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.
Abstract: A technique is presented to determine the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs, for use in the development of electrostatic discharge (ESD) protection circuits. Test structures from a fully salicided, LDD MOS process were characterized with a transmission line pulse generator to obtain the snapback voltages and the second-breakdown trigger currents (I/sub t2/) Good correlations are shown between I/sub t2/ and the human body model (HBM) ESD damage thresholds. It was seen that homogeneous current injection in the avalanching diffusions is imperative for good second breakdown behavior. A simplified thermal model, with second breakdown as the boundary condition for damage, was used in the extraction of the effective junction depth, depletion width, and transistor width under high-current conditions. Experimental data obtained for the power-to-failure as a function of the time-to-failure showed a good fit to the model. A possible extension of the technique for the use of DC characterization to monitor ESD behavior is presented. >
TL;DR: The finite element methods (FEM) calculations reveal that a cMUT operating in this new regime, between collapse and snapback voltages, possesses a coupling efficiency higher than a cWU operating in the conventional regime below its collapse voltage.
Abstract: We report on a new operation regime for capacitive micromachined ultrasonic transducers (cMUTs). Traditionally, cMUTs are operated at a bias voltage lower than the collapse voltage of their membranes. In the new proposed operation regime, first the cMUT is biased past the collapse voltage. Second, the bias voltage applied to the collapsed membrane is reduced without releasing the membrane. Third, the cMUT is excited with an ac signal at the bias point, keeping the total applied voltage between the collapse and snapback voltages. In this operation regime, the center of the membrane is always in contact with the substrate. Our finite element methods (FEM) calculations reveal that a cMUT operating in this new regime, between collapse and snapback voltages, possesses a coupling efficiency (k/sub T//sup 2/) higher than a cMUT operating in the conventional regime below its collapse voltage. This paper compares the simulation results of the coupling efficiencies of cMUTs operating in conventional and new operation regimes.