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Showing papers on "Snapback published in 1988"


Journal ArticleDOI
TL;DR: In this paper, the authors studied the effect of contact processes on ESD and found that both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the failure threshold of the NMOS transistor.
Abstract: The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi/sub 2/ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi/sub 2/ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage. >

76 citations


Patent
25 Nov 1988
TL;DR: In this article, the source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities, resulting in a device with high snapback voltages.
Abstract: A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.

30 citations


Journal ArticleDOI
F.K. Baker1, J.R. Pfiester1
TL;DR: In this article, the influence of tilted source-drain implants on device reliability was examined using two-dimensional process and devices simulations to explain the physical origins of high-field effects such as impact ionization and bipolar snapback.
Abstract: Asymmetries in MOSFET high-field effects, such as impact ionization and bipolar snapback, are used to examine the influence of tilted source-drain implants on device reliability. Several process variables, including source-drain implant conditions and anneal time, are varied to determine how they affect these asymmetries. Using two-dimensional process and devices simulations to explain the physical origins of these effects, the lightly doped drain (LDD) structure is shown to offer some immunity to tilt-angle-induced reliability problems. These results are used to suggest guidelines for the design of the LDD structure. >

18 citations


Journal ArticleDOI
B.A. Beitman1
TL;DR: In this article, a model of n-channel MOSFET breakdown, in a p-well, is proposed based on experimental measurements, which identifies three parasitic bipolar transistors that generate two independent breakdown paths.
Abstract: A model of n-channel MOSFET breakdown, in a p-well, is proposed based on experimental measurements. The model identifies three parasitic bipolar transistors that generate two independent breakdown paths. The breakdown path is dependent on the biasing conditions, the relative parasitic bipolar transistor gain, and the drain avalanche breakdown. Typical biasing of the n-channel MOSFET will result in a breakdown path, and hence snapback sustaining voltage, which is a function of the gate length. While this result is similar to that found in previous studies of snapback on bulk substrates, there is an additional component of current present at the source due to the parasitic vertical bipolar transistor created by the p-well. Another separate parasitic vertical bipolar transistor can lead to an alternative breakdown path when the n-substrate is grounded or left floating. This alternative breakdown path is independent of the gate length for long channel lengths and dependent for short channel lengths. Experimental data and characterization results are presented from two Harris 5-V CMOS processes. >

17 citations