Showing papers on "Snapback published in 1991"

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

Abstract: A technique is presented to determine the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs, for use in the development of electrostatic discharge (ESD) protection circuits. Test structures from a fully salicided, LDD MOS process were characterized with a transmission line pulse generator to obtain the snapback voltages and the second-breakdown trigger currents (I/sub t2/) Good correlations are shown between I/sub t2/ and the human body model (HBM) ESD damage thresholds. It was seen that homogeneous current injection in the avalanching diffusions is imperative for good second breakdown behavior. A simplified thermal model, with second breakdown as the boundary condition for damage, was used in the extraction of the effective junction depth, depletion width, and transistor width under high-current conditions. Experimental data obtained for the power-to-failure as a function of the time-to-failure showed a good fit to the model. A possible extension of the technique for the use of DC characterization to monitor ESD behavior is presented. >

Output pad electrostatic discharge protection circuit for mos devices

Abstract: A circuit protects the series coupled PMOS-NMOS transistor output stage, input stage or input/output stage commonly found in a CMOS device from output pad ESD, whether or not the CMOS device is mounted in a circuit board or coupled to a power source. The circuit includes a second PMOS transistor whose output leads are coupled between the output pad and the gate of the output NMOS transistor, and also includes a resistor coupled between the gate of this second PMOS transistor and a voltage source node. A positive potential ESD at the output pad will turn on the second PMOS transistor, thereby coupling positive ESD potential to the gate of the output NMOS transistor. This causes the output NMOS transistor to turn on, avoiding the "snapback" mode destruction that would occur if the second PMOS transistor were not present. The resistor cooperates with the intrinsic capacitance present at the gate of the second PMOS transistor to form an RC filter that prevents noise transients coupled to this gate from turning on the second PMOS transistor. A second preferred embodiment is a protective circuit that includes the above described series coupled output PMOS, NMOS transistors, the second PMOS transistor, and the resistor. This embodiment provides output pad ESD protection to other circuits (drivers, for example) coupled to the input gate of the output transistors, or circuits (input buffers, for example), coupled to the output pad.

A latch phenomenon in buried N-body SOI NMOSFET's

Abstract: The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V/sub GS/ is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current. >

Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation

Abstract: A two-dimensional finite-difference simulator for silicon-on-insulator (SOI) MOSFETs is presented. The simulator is derived from the MINIMOS4 simulator and incorporates additional features which permit the characterization of the bipolar snapback effect, which has been observed as a limiting feature in ultra-thin-film transistors. The snapback effect is illustrated as a hysteresis mechanism whereby, for a given bias condition, there are two different solutions to the semiconductor equations, depending on the starting condition. Examples of the application of the simulator to predict breakdown voltage in submicrometer devices are considered. Excellent agreement with measured values of breakdown voltage has been achieved for submicrometer n-channel transistors, both with and without the use of lightly doped drains. >

A comparison of base current reversal and bipolar snapback in advanced n-p-n bipolar transistors

Abstract: It is argued that base current reversal in an advanced n-p-n bipolar transistor arises from the same physical mechanism as classical bipolar snapback. Measurements of the bipolar snapback voltage, BV/sub CE0/, and of the collector-emitter voltage required for base current reversal, V/sub CE/Br/ are identical over a range of variation in transistor design and over more than eight orders of magnitude in collector current. The minimum or sustaining values of BV/sub CE0/, or V/sub CE/Br/, should be used for the purposes of bipolar device design rather than the larger trigger value measured at very low current levels. The former is an indication of electric field strength in the collector-base depletion region while the latter is a monitor of the level of the nonideal base current component. Measurement of base current reversal provides a more consistent and less destructive technique of characterizing bipolar sustaining voltage. >

An analytical model for snapback in n-channel SOI MOSFET's

Abstract: An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3- mu m epi film. >

MOSFET flyback-diode conduction and dV/dt effects in power ICs in low-voltage motor control applications

Abstract: In a power IC, the direct drive of a low-voltage motor by one or more MOSFET half-bridges results in inductive-flyback diode conduction during switching transitions. PISCES computer simulation reveals that this diode current in an integrated lateral MOSFET manifests itself as parasitic bipolar conduction where a substantial fraction of the carriers injected from the forward-biased drain-to-body junction is collected by the transistor's source. The physics of parasitic bipolar turn-off, or recovery, is shown to depend on the application. The resulting driving-point conditions can be classified into one of three possible diode recovery scenarios. In either natural or synchronously clamped recovery, high dV/dt is prevented by the inductive time constant of the motor. In forced recovery operation, fast diode turn-off and high dV/dt results from shoot-through between the recovering diode and the MOSFET within a given half-bridge. analysis reveals that a high dV/dt leading to minority carrier injection from the source slows the forced reverse-recovery time without leading to destructive snapback. >

Pre-turn-on source bipolar injection in graded NMOSTs

Abstract: The influence of the pre-turn-on source bipolar injection on graded NMOST breakdown characteristics is investigated. Double-implanted As-P (n/sup +/n/sup -/) source-drain NMOS structures (DD NMOSTs) with different effective channel lengths, ranging from 1.15 to 9.15 mu m, are measured. Using a simple, but accurate, semi-empirical model for the transistor operating in the breakdown region, it is shown that the DD NMOST snapback voltage is substantially decreased due to the enhanced pre-turn-on source electron emission current. >

Reoxidized nitrided oxides (RNO) for latent ESD-resistant MOSFET dielectrics

Abstract: n-channel MOSFETs with reoxidized nitrided oxides (RNOs) are compared to conventional oxides with respect to their susceptibility to latent damage from electrostatic discharge (ESD) and ESD-like events. It is shown, using both ESD events and simulated ESD events by snapback, that the RNO devices have substantially better resistance to latent damage from such events. The increased resistance is explained by the robustness of the nitrided oxides both to interface state generation and to oxide trap creation by hot-hole injection. It is concluded that, along with hot-carrier resistance, the RNO robustness to latent ESD damage is another advantage of this technology. >

Triggering and sustaining of snaphack in MOSFETs

Abstract: This paper analyses the phenomenon of snapback (negative resistance portion of the output characteristic) in MOSFETs. It shows that the expansion of the base of the parasitic bipolar transistor provides the necessary basis for the understanding of the snapback mechanism. It also offers simple criteria for the snapback triggering and sustaining which have been lacking to date.

Problems and issues in SOI CMOS technology

Abstract: Various issues in SOI (silicon-on-insulator) CMOS technology are reviewed. In particular, it is pointed out that from a device standpoint, the 'nice' properties of FD SOI MOSFETs, such as high saturation current and sharp subthreshold slope, are now overshadowed by unwanted floating substrate effects. The most serious of these is caused by the lateral bipolar, which causes snapback in long-channel devices. The snapback reduces to low BVDS in shorter-channel devices. There are indications that SOI may have a better BVDS than bulk for L >

A differential-height-mesa buried body tie SOI process

Abstract: A low-area penalty method of contacting the floating body of thin-film SOI (silicon-on-insulator) devices has been devised. By contacting the otherwise floating body, its potential can be fixed and the well-documented issues of bipolar snapback and kink arising from impact ionization may be mostly or entirely mitigated. This body tie is fabricated under a conventional LOCOS field isolation structure. An added benefit of this process approach is that mesas of different thicknesses may be readily fabricated so that a mixture of fully depleted and partially depleted transistors can be built on a common substrate simultaneously. >