Showing papers on "Snapback published in 1994"

Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions

Abstract: We present the underlying mechanisms of second breakdown in deep submicron nMOS transistors under high current snapback conditions The onset of second breakdown is shown to be determined by a rapid increase in the thermally generated component of the substrate (base) current Simplified simulation methodologies for evaluating high current robustness using isothermal device simulations are demonstrated and good correlations with experimental data have been obtained >

Compact electro‐thermal simulation of ESD‐protection elements

Abstract: Numerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester parasitics and additional parasitic elements in the circuitry have been investigated. Compact electro-thermal models for single protection elements (diodes and snapback nMOSFETs) have been developed. They help to explain differences between expected ESD-hardness and HBM-failure thresholds of protection structures.

The effect of body resistance on the breakdown characteristics of SOI MOSFET's

Abstract: The drain-source breakdown of (nonfully depleted) SOI MOSFET's is analyzed with attention paid to the body (to source) resistance, R/sub B/. Simple but physical characterizations of the holding voltage and the snapback voltage in terms of device parameters are derived. The physical insight afforded reveals that the snapback characteristic is an inherent effect of finite R/sub B/. The holding voltage increases with decreasing R/sub B/, but for submicron devices the increase is not significant unless R/sub B/ is decreased well below values achieved with typical intrinsic body-to-source ties having acceptable (limited) widths. >

Analytical Calculation of Avalanche and Thermal Snapback Points in Bipolar Transistors

Abstract: Analytical calculations of thermal-and avalanche snapback points are given to predict when thermal runaway in a bipolar transistor is initiated. These snapback points are used to construct the Safe Operating Area of the transistor in the case of a current and a voltage controlled base.

An electrothermal circuit simulation using an equivalent thermal network for electrostatic discharge (ESD)

Abstract: This paper describes an electrothermal circuit simulation using an equivalent thermal network for electrostatic discharge (ESD). Electrothermal transient characteristics in ESD protection devices are clarified in detail by modeling of complicated snapback behavior and thermal modeling in the multiple layer. The new model allows the simulation for the damage region and failure thresholds of n-MOSFETs under ESD stress conditions. >

Compact electro-thermal simulation of ESD-protection elements

Abstract: Numerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester parasitics and additional parasitic elements in the circuitry have been investigated. Compact electro-thermal models for single protection elements (diodes and snapback nMOSFETs) have been developed. They help to explain differences between expected ESD-hardness and HBM-failure thresholds of protection structures.

Input-output protection circuit

Abstract: PURPOSE:To make an overvoltage from an input-output terminal escape effectively and thereby to enable protection of an internal circuit by making a snapback voltage of a parasitic MOS transistor lower than a breakdown voltage of a junction part of a diffused layer thereof. CONSTITUTION:A P channel stopper 3 having P-type impurity concentration of about 1X10 or above is formed under an LOCOS oxide film 9. The LOCOS oxide film 9 and an interlayer insulation film 10 are made a gate oxide film and an aluminum electrode 6 is formed on the interlayer insulation film 10, and made a gate electrode. Moreover, an N area of diffused layer having N-type impurity concentration of 1X10 cm or above is formed as a source and drain 5. Thereby a parasitic MOS transistor wherein an SD breakdown voltage is lower than the breakdown voltage of the diffused layer is obtained. Two parasitic MOS transistors for one input-output terminal are adopted as one set and an input-output protection circuit is formed for each input-output terminal.