Showing papers on "Snapback published in 1998"

Snapback repellers as a cause of chaotic vibration of the wave equation with a van der Pol boundary condition and energy injection at the middle of the span

Abstract: A wave equation on a one-dimensional interval I has a van der Pol type nonlinear boundary condition at the right end. At the left end, the boundary condition is fixed. At exactly the midpoint of the interval I, energy is injected into the system through a pair of transmission conditions in the feedback form of anti-damping. We wish to study chaotic wave propagation in the system. A cause of chaos by snapback repellers has been identified. These snapback repellers are repelling fixed points possessing homoclinic orbits of the non-invertible map in 2D corresponding to wave reflections and transmissions at, respectively, the boundary and the middle-of-the-span points. Existing literature [F. R. Marotto, J. Math. Anal. Appl. 63, 199–223 (1978)] on snapback repellers contains an error. We clarify the error and give a refined theorem that snapback repellers imply chaos. Numerical simulations of chaotic vibration are also illustrated.

Non-uniform triggering of gg-nMOSt investigated by combined emission microscopy and transmission line pulsing

Abstract: The triggering of grounded gate nMOSFET (gg-nMOS) and field-oxide devices (FOXFETs), essential for optimized ESD protection design, is addressed by TLP-pulsed emission microscopy. Current nonuniformity and instability effects in snapback operation under DC and TLP conditions are demonstrated. The comprehensive correlation of emission and electrical behaviour allows an improved interpretation of device operation. Technological influences on the trigger uniformity are discussed.

Integrated semiconductor circuit with protective structure for protection against electrostatic discharge

Abstract: An integrated semiconductor circuit includes a protective structure for protection against electrostatic discharge. The protective structure is disposed between a terminal pad and the integrated semiconductor circuit and is connected to at least one busbar. The protective structure includes transistors of different types with reciprocal coupling of the collector terminals and base terminals to form a thyristor structure. Integrated vertical npn switching transistors are used as protective elements, the bases of which are driven by integrated pnp driving transistors. The gain factor of the driving transistors is small enough to avoid the triggering of the parasitic thyristor with undesirable snapback of the high current characteristic curve at the sustaining voltage. A buried layer having partial regions with a higher doping concentration than regions of the buried layer outside the partial regions. The buried layer has a very low resistance, which results in homogenization of the current flow in the event of breakdown. The turn-on voltage of the active protective element is additionally set by suitable selection of the base width of the driving transistors.

Simulation of complete CMOS I/O circuit response to CDM stress

Abstract: Enhanced compact modeling is implemented in a commercial simulator to study CMOS circuit response to charged device model (CDM) stress. Procedures for characterization of transistor snapback, oxide breakdown, and package and tester parasitics are detailed. Application to 0.25 /spl mu/m technology SRAM I/O circuits demonstrates effectiveness in analyzing CDM response and quantitatively predicting withstand levels.

Esd protection circuit immune to latch-up during circuit operation

Abstract: An ESD protection circuit of the present invention comprises a semiconductor controlled rectifier and at least one diode connected in series. The series-connected semiconductor controlled rectifier and diode are electrically coupled between a pair of circuit nodes. Even though the semiconductor controlled rectifier enters snapback during circuit operation the diode can be utilized to increase a holding voltage between the pair of circuit nodes. The required number of diodes is based upon the design consideration so that proper trigger voltage and holding voltage can be acquired. The semiconductor controlled rectifier can be a lateral semiconductor controlled rectifier, a low voltage triggering semiconductor controlled rectifier, or a floating-well semiconductor controlled rectifier.

A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy

Abstract: This paper presents the use of circuit simulations in understanding of the internal ESD (electrostatic discharge) failure observed in a 06 /spl mu/m CMOS technology product chip Simulation of the ESD current paths near the V/sub dd/ pin are performed and the cause of ESD failure is identified using a circuit simulator that includes the MOS snapback models These simulations are used to suggest issues to be considered in design of protection circuits to avoid this type of internal ESD failure

Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 /spl mu/m CMOS technology

Abstract: An electrostatic discharge (ESD) evaluation of a silicided 0.25 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technology is carried out by HEM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

Dynamic substrate-coupled electrostatic discharging protection circuit

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source V DD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

ESD structure having an improved noise immunity in CMOS and BICMOS semiconductor devices

Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (V ss ) and/or V cc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n + -type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n + source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

A base resistance controlled thyristor with the self-align corrugated p-base

Abstract: A new base resistance controlled thyristor with the self-aligned corrugated p-base, entitled CB-BRT, is proposed and fabricated in order to suppress the snapback phenomenon and to increase the maximum controllable current. The corrugated p-base is formed by self-aligned boron diffusion using the gate polysilicon as a mask. The new device reduces the snapback effectively by decreasing the latching current without sacrificing the forward voltage. The regenerative thyristor action is suppressed during the turn-off period so that the maximum controllable current increases in the CB-BRT.

Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer

Abstract: This paper presents a novel technique to eliminate non-simultaneous triggering effects in finger-type ESD protection transistor using SiGe heterojunction buried layer structures. It is confirmed that lower snapback voltage and maximum lattice temperature are obtainable in the new structure based on device simulation. As a result, current localization and lattice overheating of a finger-type protection transistor caused by process variations can be avoided in this structure.

Utilizing design of experiments, Monte Carlo simulations and partial least squares in snapback elimination

Abstract: The first test structures built on a newly developed semiconductor process revealed that product could be susceptible to an operational fault called the snapback condition. The process architect identified five factors that might be adjusted to greatly reduce the occurrence of snapback. A response surface type of experiment was run on the process simulator so that the ideal combination of settings for these five factors could be identified. Monte Carlo simulations were then run at the new settings for those process factors. The data from the Monte Carlo simulations were analysed using partial least squares to identify the process variables that would be most critical to control in maintaining a snapback-resistant process. The new settings were confirmed on actual product. © 1998 John Wiley & Sons, Ltd.