Showing papers on "Snapback published in 2001"

Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage

Abstract: The physical mechanisms that influence the triggering and holding voltage in a DMOS transistor in CMOS smart power technology are investigated. We demonstrate that a high and a low holding voltage device can be designed by changing the lateral bipolar base distance and that also the trigger voltage can be easily tuned. The layout variation that controls the holding voltage also leads to a different snapback mechanism and a different current flow through the device. Excellent ESD capabilities of 16-20 mA//spl mu/m width have been achieved.

Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

Abstract: A thorough analysis of the physical mechanisms involved in a vertical grounded-base n-p-n bipolar transistor (VGBNPN) under electrostatic discharge (ESD) stress is first carried out by using two-dimensional (2-D) device simulation, transmission line pulse measurement (TLP) and photoemission experiments. This analysis is used to account for the unexpected low value of the VGBNPN snapback holding voltage under TLP stress. A compact model based on a new avalanche formulation resulting from the exact resolution of the ionization integral is therefore proposed.

Snapback behavior of the postbreakdown I–V characteristics in ultrathin SiO2 films

Abstract: With the I–V measurement technique that forced a current to an ultrathin gate oxide and measured the voltage drop, a snapback phenomenon, ie, the gate oxide was switched from a higher-impedance state to a lower-impedance state suddenly, was observed during the postbreakdown I–V measurement The snapback could be triggered at a very low measurement current Single or multiple snapbacks have been observed, and it was found that the occurrence of snapback was a random event The snapback is explained in terms of the formation of an additional percolation path due to the neutralization of negatively charged traps or the generation of neutral electron traps at certain strategic positions during the measurement

Electrostatic discharge protection circuit

Abstract: In an electrostatic protection circuit of the present invention, a trigger voltage for causing snapback operation in MOSFET is reduced and circuit elements with low breakdown voltages can be protected. A protection nMOSFET having a drain connected to an input/output terminal and a source and a substrate that are grounded is provided. A diode array, composed of at least one diode, is connected in series in a forward direction between the gate of the protection nMOSFET and the input/output terminal. Finally, a resistor is connected between the gate of the protection nMOSFET and ground.

Snapback behaviour and its similarity to the switching behaviour in ultra-thin silicon dioxide films after hard breakdown

Abstract: Snapback behaviour, with well-defined conduction states involved, has been observed in the ramped-current current-voltage (I-V) characteristics of ultra-thin silicon dioxide films after the occurrence of hard breakdown. The comparison of the snapback behaviour with the switching behaviour observed in the ramped-voltage measurement shows that the two behaviours are similar, suggesting that they can be explained by the same mechanism. The I-V relationship of each conduction state involved in either the snapback or the switching behaviours was found to follow a power law. These observations are consistent with the percolation model, and they can be easily explained in terms of the on/off of conductive percolation paths due to detrapping/trapping or neutral trap generation at certain SiO2 lattice sites (strategic positions) during the measurements.

Investigation of Body-Tie Effects on Ion Beam Induced Charge Collection in Silicon-On-Insulator FETs Using the Sandia Nuclear Microprobe

Abstract: Silicon-on-insulator (SOI) technology exhibits three main advantages over bulk silicon technology for use in radiation environments. (1) SOI devices are immune to latchup, (2) the volume of the sensitive region (body) and hence total charge collection per transient irradiation is much reduced in SOI devices and (3) the insulating layer blocks charge collection from the substrate (i.e., no funneling effect). This effectively raises the single event upset (SEU) threshold for the SOI device. However, despite their small active volume SOI devices are still vulnerable to single event effects (SEE). Inherent in the SOI transistor design is a parasitic npn bipolar junction transistor (BJT), where the source-body-drain acts as an emitter-base-collector BJT. An ion strike to a floating (not referenced to a specific potential) body creates a condition where the excess minority carriers in the drain-body cause the parasitic BJT to turn on and inject more charge into the drain than was deposited in the device by the ion. In extreme cases the floating body effect (FBE) can trigger a high-current state called single-event snapback (SES) where channel conduction is sustained indefinitely through regenerative electron-impact ionization near the drain junction. Tying the body to the source limits the emitter-base current and reduces the sensitivity of the device to single ion strikes. Unfortunately, the body-tie loses effectiveness with distance due to resistivity, and in regions far enough from the tie the BJT is still in effect. Using the Sandia nuclear microprobe we have created charge collection maps on Sandia CMOS6rs SOI FETs of varying channel widths. These devices have body ties at both ends of the channel region. Results clearly demonstrate that distance of the ion strike from the body tie has an inverse effect upon charge collection and SES sensitivity due to the resistivity of the channel. Experimental results compare well with DAVINCI simulations and electrically induced snapback thresholds. In addition, an interesting saturation effect of SES versus the amount of injected charge is observed.

Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N+ region blocking

Abstract: In a n+ snapback device, saturation current is limited by using one or more NLDD current blocking regions. This limits the snapback saturation current, while avoiding current stratification by providing for current spreading, and thus avoiding localized heating problems

Extraction of eleven model parameters for consistent reproduction of lateral bipolar snapback high-current I-V characteristics in NMOS devices

Abstract: A series of literature models originally devoted to the second breakdown trigger current I/sub t2/ in a grounded-gate NMOS transistor can further find promising potential in handling high-current I-V due to lateral bipolar snapback. This is achieved primarily by building significant linkage between bipolar current-gain /spl beta/-related parameters: 1) the collector-to-base junction voltage dependencies A/sub 1/ and A/sub 2/ of the medium-level injection /spl beta/ roll-off factor; 2) the high-level /spl beta/ roll-off factor A/sub 3/; and 3) the collector-to-base junction voltage dependencies A/sub 4/ and A/sub 5/ of the collector corner current at the onset of high-level /spl beta/ roll-off. The new parameters A/sub 1/ to A/sub 5/ enable a consistent I-V solution along with other existing six model parameters such as the substrate resistance R/sub sub/ and its conductivity modulation factor A/sub /spl tau//, the impact ionization coefficients K/sub 1/ and K/sub 2/, and the emitter series resistance R/sub e/ and collector series resistance R/sub c/. Parameter extraction except R/sub c/ is thoroughly performed using only the parametric analyzer, and opposed to the traditional procedure, impact ionization coefficients and current gains are all assessed without entering the snapback regime. Remarkably, not only excellent agreements are obtained, but also bipolar snapback I-V measured under the current pulsing condition can be separated into two distinct parts: medium- and high-level injection region. This is quite effective under R/sub e/=R/sub c/. Series resistance, although having very low value, is not to be absent under the high-level injection conditions.

Polysilicon bounded snapback device

Abstract: A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage once it snaps back into bipolar operation mode after its trigger point is achieved. The snapback device includes the advantage of a low breakdown voltage which enables the snapback device to snap back into bipolar mode before damage is done to active circuit components due to their breakdown voltages being exceeded. The snapback device includes n+ active areas formed within a p-well substrate region and each active area includes a polysilicon film overlapping the active area but insulated therefrom by a dielectric film. Each n+ active area and polysilicon film are coupled by a conductive film and the components combine to form one electric node. One electric node of the snapback device is coupled to I/O terminals of the device and the other is coupled to ground or a power supply.

A Novel EST with Trench Electrode to Immunize Snab-back Effect and to Obtain High Blocking Voltage

Abstract: A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improves snapback which leads to a lot of problems of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor (EST) with trench electrode has been proposed for improving snab-back effect. It is observed that the forward blocking voltage of the proposed device is 745V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

Integrated circuit with semiconductor comprising a structure for protection against electrostatic discharges

Abstract: An integrated semiconductor circuit includes a protective structure for protection against electrostatic discharge. The protective structure is disposed between a terminal pad and the integrated semiconductor circuit and is connected to at least one busbar. The protective structure includes transistors of different types with reciprocal coupling of the collector terminals and base terminals to form a thyristor structure. Integrated vertical npn switching transistors are used as protective elements, the bases of which are driven by integrated pnp driving transistors. The gain factor of the driving transistors is small enough to avoid the triggering of the parasitic thyristor with undesirable snapback of the high current characteristic curve at the sustaining voltage. A buried layer having partial regions with a higher doping concentration than regions of the buried layer outside the partial regions. The buried layer has a very low resistance, which results in homogenization of the current flow in the event of breakdown. The turn-on voltage of the active protective element is additionally set by suitable selection of the base width of the driving transistors.

Development of substrate-pumped nMOS protection for a 0.13∝m technology

Abstract: A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complimented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time. HBM data that shows the Substrate-Pumped nMOS can provide dramatically higher protection than estimated from conventional It2 measurements. This motivates improved ESD circuit development. The nMOS clamp transistor is characterized as an actively biased LNPN, which is how it is used in a Substrate-Pumped protection circuit. A system-oriented approach to circuit development is described that is based upon empirical characterization of well-defined circuit components under conditions approximating ESD.

Magnetic snapback sensor circuit and electrostatic discharge circuit using same

Abstract: A magnetic snapback sensor circuit for sensing current transients imposed on the snapback circuit including a current conductor loop; a conductor carrying current from a snapback circuit subject to current transients and intersecting with the conductor loop for magnetically generating a current in the loop; and a current detector circuit for generating an output responsive to the current flowing in the loop induced by a current transient.

Parasitic bipolar transistor model using generated-hole-dependent base resistance

Abstract: An accurate parasitic bipolar transistor model is indispensable for the evaluation of ESD immunity. Injected electrons are well known to modulate base resistance, but we found that it is not true during snapback because the electric field associated with injected electrons is compensated by the holes generated in the drain region. We therefore developed a new base resistance model that depends on generated holes as well as injected electrons. Here we show that this model can account for the Gummel plot and the snapback characteristics simultaneously. Furthermore, we developed analytical modes for prominent features of snapback characteristics and clarified the dependence of snapback characteristics on various parameters.

Gate-driven or gate-coupled electrostatic discharge protection circuit

Abstract: A kind of gate-driven or gate-coupled electrostatic discharge (ESD) protection circuit is disclosed in the present invention. The first voltage source and the second voltage source are provided to the ESD protection circuit. The ESD protection circuit includes the first resistor, a capacitor, an inverter, the second resistor, the first NMOS, and the second NMOS. In the invention, the voltage division principle from the inverter output resistance and the first NMOS output resistance is used to make the gate electrode of the second NMOS have an appropriate voltage to speed the parasitic BJT conduction of the second NMOS for entering the Snapback region so as to even effectively release the instantaneously large current generated by the ESD pulse. By appropriately adjusting the ratio between the inverter output resistance and the first NMOS output resistance, it is capable of controlling the biased voltage on the gate of the second NMOS to avoid damage on the gate oxide layer of the second NMOS generated due to too high voltage.

Instability in post-breakdown conduction in ultra-thin gate oxide

Abstract: Both switching and snapback between two well-defined states (a lower impedance state and a high impedance state) in the post-breakdown conduction in ultra-thin silicon dioxide films have been observed, and a comparison between them was made. The current-voltage relationship of each state was found to follow a power law for both the switching and snapback. The switching and snapback can be explained in terms of the on/off state of a second conductive percolation path of neutral oxide traps due to the de-trapping/trapping or neutral trap generation at certain SiO/sub 2/ lattice sites (strategic positions) during the measurements.

CMOS ESD clamp with input and separate output voltage terminal for ESD protection

Abstract: In a snapback NMOS ESD protection structure, the output voltage presented to an internal circuit for ESD protection is limited by providing for a separate output terminal at a lower voltage than the input terminal. The voltage drop between the two terminals is achieved by connecting the input and output terminals to different parts of a ballast region of the structure and using the saturation resistance of the portion of the ballast region between the terminals to achieve the voltage drop.