Showing papers on "Snapback published in 2003"

Radiation effects in SOI technologies

Abstract: Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

A new regime for operating capacitive micromachined ultrasonic transducers

Abstract: We report on a new operation regime for capacitive micromachined ultrasonic transducers (cMUTs). Traditionally, cMUTs are operated at a bias voltage lower than the collapse voltage of their membranes. In the new proposed operation regime, first the cMUT is biased past the collapse voltage. Second, the bias voltage applied to the collapsed membrane is reduced without releasing the membrane. Third, the cMUT is excited with an ac signal at the bias point, keeping the total applied voltage between the collapse and snapback voltages. In this operation regime, the center of the membrane is always in contact with the substrate. Our finite element methods (FEM) calculations reveal that a cMUT operating in this new regime, between collapse and snapback voltages, possesses a coupling efficiency (k/sub T//sup 2/) higher than a cMUT operating in the conventional regime below its collapse voltage. This paper compares the simulation results of the coupling efficiencies of cMUTs operating in conventional and new operation regimes.

Phase change access device for memories

Abstract: A memory may have access devices formed using a chalcogenide material The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed In the case of phase change memory elements, the snapback voltage may be less than the threshold voltage of the phase change memory element

Current filament movement and silicon melting in an ESD-robust DENMOS transistor

Abstract: HBM and TLP results for an 80 V DENMOS transistor are analyzed and simulated. The current is found to initially crowd into a small filament (to achieve its 2D 18.5 mA/mum snapback current density) which moves to cooler regions during the extent of the pulse. The mechanism and controlling factors for this filament movement, including lateral base-pumping, are investigated and quantified for general transistors. For the particular transistor, silicon melting (or some high-temperature electrical property change) is thereby deemed likely. A 3x improvement in the TLP damage current by adding parallel capacitance is also explained.

PMOS electrostatic discharge (ESD) protection device

Abstract: A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

A fast switching segmented anode NPN controlled LIGBT

Abstract: An ultrafast low energy loss lateral insulated gate bipolar transistor (LIGBT) with a novel segmented anode structure is demonstrated. The anode comprises segments of p/sup +/ and n/sup +//p (n/sup +/ region formed within a p-type region) along the width of the device. By simply varying the ratio of these segments the tradeoff between conduction and switching losses can be varied. Unlike an anode shorted structure this does not exhibit an undesirable snapback in its on-state characteristics. This structure is simple to realize in a CDMOS process without the need for any additional process steps.

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

Abstract: The layout dependence on ESD robustness of NMOS and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the energy band diagrams.

Method for implementing electro-static discharge protection in silicon-on-insulator devices

Abstract: The present invention is a method and apparatus whereby two NMOS or PMOS devices connected in series in a stacked gate configuration formed on SOI exhibit improved ESD response characteristics. The shared source-drain region between the two devices is formed to have a dopant depth in the shared region that does not extend through the silicon layer to the BOX layer. This provides a common body for the two devices, and thus a single parasitic bipolar transistor is formed between the drain of one NMOS or PMOS device and the source of the second NMOS or PMOS device. Simultaneous snapback occurs for the two devices through the common body. A further embodiment includes a method of forming two or more stacked gate NMOS or PMOS devices on SOI. The method includes protecting the shared source-drain region between two NMOS or PMOS devices during a final doping step and silicide processing.

Pfet-based esd protection strategy for improved external latch-up robustness

Abstract: A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.

Decay and snapback in superconducting accelerator magnets

Abstract: This thesis deals with the explanation and compensation of the effects ‘decay’ and ‘snapback’ in superconducting accelerator magnets, in particular in those used in the new Large Hardron Collider at CERN. During periods of constant magnet excitation, as for example during the injection of particles in the storage ring, the magnetic field in superconducting accelerator magnets shows a decay behavior. As soon as the particles are accelerated, the magnets are ramped, and the magnetic field ‘snaps back’ to the original hysteresis curve. Decay and snapback affect the beam in the machine and have to be compensated precisely in order to avoid losses of particles.

Co-design methodology to provide high ESD protection levels in the advanced RF circuits

Abstract: This paper describes an approach to design ESD protection for integrated Low Noise Amplifier (LNA) circuits, used in narrowband transceiver front-ends. The RF constraints on the ESD devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimize. The method is applied to the design of 0.25 mum CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional high capacitive ggNMOS snapback devices.

ESD phenomena in interconnect structures

Abstract: Interconnect forms a part of all ESD protection networks. ESD discharges can cause both latent and permanent damages in interconnect structures. ESD discharges, that barely affect the resistance of a structure, can reduce the electromigration lifetime of metal structures by more than a factor 100. Also snapback behavior, which limits the ESD robustness of silicon based interconnect structures, is observed. With this knowledge designs can be optimized for area and robustness.

Snapback circuit model for cascoded NMOS ESD over-voltage protection structures

Abstract: This paper presents an equivalent circuit snapback model for the ESD domain operation of merged cascoded NMOS devices. The model reflects the specific breakdown operation of the structure at different gate bias conditions. An example for optimisation of the ESD behaviour of an output driver, utilising this protection device, is presented.

Electrical fuse for integrated circuits

Abstract: An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a gate-source coupled MOS transistor. If the MOS transistor is unprogrammed, then the resistive element ensures that the programmable transistor is turned off during read operations. However, when a programming voltage is applied across the source and drain terminals of the programmable transistor, the resistive element allows the programming voltage to be capacitively coupled to the gate of the programmable transistor from its drain. This turns the programmable transistor on, thereby reducing the snapback voltage of the programmable transistor, and hence, the required programming voltage. Once the snapback mode is entered, current flow through the programmable transistor increases until thermal breakdown occurs and the programmable transistor shorts out. The programmable transistor will then behave as a constant-on transistor during all subsequent read operations.

Transistor circuits for switching high voltages and currents without causing snapback or breakdown

Abstract: A high voltage/high current switching circuit (200), without snapback or breakdown, comprises a first set of series-connected transistors that includes a plurality of transistors (MX30-MX63, MN0) to switch a high voltage without inducing snapback or breakdown ; and a second set of series-connected transistors that includes at least two transistors (MP2-MP3) to switch a high current. The first and second sets of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector (410) is connected to an output (Vep) of the first and second sets of series-connected transistors. The output (Vepup) of the voltage detector is coupled to the enabling means (500-2, 500-3).

Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design

Abstract: The objective of this study is to find a generic design solution for the cascoded snapback NMOS that delivers robust operation and eliminates the requirement for an additional ESD implant. In addition, the research goal of this study is to understand the physical failure mechanism, taking into account the non-linear effects of NMOS snapback, and to provide, at a minimum, a phenomenological explanation of the observed trends resulting from the analysis of Si based experiments.

Equivalent Circuit Model of ESD Protection Devices

Abstract: In this paper, we propose an equivalent circuit model that describes the snapback characteristics of ESD (Electrostatic Discharge) protection devices constructed using MOS transistors. Our goal was to predict the ESD immunity of CMOS integrated circuits using circuit simulations. The ESD immunity can be predicted from the high-current behavior (the snapback characteristics) of the protection devices. In this paper, we explain our equivalent circuit model, which includes a parasitic bipolar transistor with a generated-hole-dependent base resistance. Because the models for parasitic elements are combined with a SPICE MOS transistor model, our model can represent the gate bias dependence of snapback characteristics. The equivalent circuit parameters are extracted from the device simulations and modified to reproduce the measured snapback characteristics of the MOS transistor. Therefore, our equivalent circuit model for MOS protection devices can be used in ESD circuit simulations.

Uniform turn-on design on multiple-finger MOSFET for ESD protection application

Abstract: An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a finger MOS transistor is trigger initially to snapback region owing to its layout or other causes, a voltage drop across the inductor or the resistor connected to the source of the finger MOS transistor is occurred and presented to gates of the other finger MOS transistors by the feedback circuit. Thus, the other finger MOS transistors are turned on.

Dynamic substrate resistance snapback triggering of ESD protection devices

Abstract: This paper describes a novel approach to design self-triggered ESD protection structures. It consists in adding a reverse biased p-n junction in the path of the current, flowing into the base of the ESD activated parasitic BIT device. As a result, the base resistance of the parasitic BIT is increased, which in turn leads to faster and more uniform snapback triggering. The ESD threshold levels for the investigated structures designed in the new approach are found to increase. MEDICI simulations, in combination with TLP and EMMI characterization are performed to study the structure operation.

Physical modeling of off-state breakdown in power GaAs MESFETs

Abstract: We have investigated the physical mechanism of off-state breakdown in GaAs MESFETs that exhibited an initial breakdown voltage shift called “walkout” and snapback in I – V characteristics. From experiments using dual-gate MESFETs under various bias stress conditions, we attributed the origin of breakdown walkout to the change in electrical properties of the surface state at the gate edge. This was confirmed by experiments using newly developed open-gate FETs whose surface state was changed from an electron trap to a hole trap in the ungated region within about 0.4 μm from the gate edges. The change in surface-state properties can be explained by assuming electron injection from the gate metal into the oxide layer and the following surface Fermi-level dynamics. To verify our breakdown walkout model, we performed a two-dimensional simulation of gate–drain breakdown in GaAs MESFETs taking into account impact ionization, tunneling, and the proposed surface-state model. Our simulation can successfully describe the experimentally observed breakdown behavior, i.e., walkout and snapback.

ESD-implant effect on protection capability of NMOS structures

Abstract: The effect of the so-called ESD-implant was studied and clarified for the complex case of cascoded snapback NMOS structures suitable for 5 V tolerant I/O applications. The critical role of the ESD implant and epi-substrate resistivity on the local maximum temperature during the stress is clarified. Physical process and device numerical analysis was used to gain greater insight into these phenomena.

Optimization of L/sub Gate/ for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

Abstract: The high-current characteristics of ggNMOS fabricated on bulk- as well as on SOI-substrates using a 0.6 /spl mu/m-CMOS technology have been simulated for different values of the gate length L/sub Gate/. Prior to the simulation, the doping profiles and physical transport parameters were calibrated with reference to measured data. The snapback differential resistance R/sub spdiff/ is found to be higher for SOI-devices. Also, an optimum value of L/sub Gate/ is determined for the bulk-substrate, yielding a minimum snapback holding voltage V/sub H/. For SOI fabrication, however, VH decreases with shrinking L/sub Gate/. We explain this behavior on the basis of the electrothermal simulation results.

Diode element and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To reduce snapback which occurs during reverse current flow in a diode element caused by breakdown SOLUTION: The diode element comprises a first semiconductor region (1) of first conductive type, a second semiconductor region (2) of first conductive type which is formed of an epitaxially grown layer being in contact with the first semiconductor region (1) with its impurity concentration being lower than that of the first semiconductor region (1), and a third semiconductor region (3) and a fourth semiconductor region (4) which are formed in the second semiconductor region (2) by sequentially introducing therein second conductive type impurities, a type counter to the first conductive type, and first conductive type impurities Snapback of the diode element (10) can be reduced by controlling current amplification with the control of a resistance value of the third semiconductor region (3) Further, variation in breakdown voltage in a large current region of the diode element (10) can be made smaller by heavily doping the first semiconductor region (1) COPYRIGHT: (C)2005,JPO&NCIPI

ESD protection cluster and method of providing multi-port ESD protection

Abstract: In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to the ports that are to be protected.

Test structures and test methodology for developing high voltage ESD protection

Abstract: In this work, test structures and a test methodology is developed to evaluate proposed silicon controlled rectifier based ESD clamps in all modes of operation. TCAD analysis is used to identify possible ESD clamp structures. Standard ESD testing on the stand-alone test structures is used to screen the ESD capability of the candidate clamps. The transmission line pulse technique, with variation in pulse rise time, is used to evaluate the dynamic triggering characteristics of a snapback based clamp and select an appropriate clamp for fast switching applications. Finally, a very efficient local ESD clamp based on a bipolar-silicon controlled rectifier in a 24 V complementary power BiCMOS smart power process is presented.

TLP analysis of 0.125 μm CMOS ESD input protection circuit

Abstract: In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a ggNMOS clamp in the input protection circuitry, then the trigger voltage, Vt1, of the ggNMOS increases. More importantly, the HBM injected current required to trigger snapback, It1, is significantly increased which unexpectedly delays the trigger of the ggNMOS secondary clamp and exposes the input receiver's thin gate oxide to excessive input pad stress voltages which results in 1-2 kV HBM leakage failures.

ESD device simulation

Abstract: This chapter discusses ESD device simulation. The fundamental equation used in numerical simulation is to provide a qualitative understanding of the prerequisites and constraints of the approaches. This chapter has restricted itself to considering only short square current pulses as discharge waveforms. The evaluation is very beneficial for an ESD engineer to optimize process technology and design at the same time. The most important findings of this chapter can be summarized as the simulation of high-current densities under ESD stress requires correct treatment of electro-thermal transport and heat flow. Correct use of the device simulator for ESD simulation requires process-technology-specific calibration of SRH generation and recombination parameters. For the simulation of a realistic temperature distribution in the device, the correct treatment of thermal boundaries is highly relevant. It has been shown that the high-current IV characteristic can properly be reproduced by device simulation. Depending on the current regime, 2D simulation may be enough, or else, 3D simulation must be applied because of current instabilities in the snapback regimes. In device simulations, there is no simple failure criterion such as an increased leakage in a measurement. ESD device simulation can be applied to a wide variety of devices besides FETs. The current-to-failure dependence obtained from 2D device simulation represents a powerful extension and improvement of the classical description using analytical expressions.