Showing papers on "Snapback published in 2005"

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs

Abstract: The holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the LCD driver ICs to be susceptible to the latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-/spl mu/m 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with power supply of 40 V.

Accessing phase change memories

Abstract: A memory (100) may include a phase change memory element (130) and series connected first (125) and second (120) selection devices. The second selection device (120) may have a higher resistance and a larger threshold voltage than the first selection device (125). In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices (120, 125) and the memory element (130) may be made of chalcogenide. In some embodiments, the selection devices (120, 125) may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models

Abstract: A novel macro model approach for modeling ESD MOS snapback is introduced. The macro model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. No external current source, which is essential in most publicly reported macro models, is included since both BSIM3vs and VBIC have formulations built in to model the relevant effects. The simplicity of the presented macro model makes behavior languages, such as Verilog-A, and special ESD equations not necessary in model implementation. This offers advantages of high simulation speed, wider availability, and less convergence issues. Measurement and simulation of the new approach indicates that good silicon correlation can be achieved.

Analysis and design of the dual-gate inversion layer emitter transistor

Abstract: The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.

ESD Scalability of LDMOS Devices for Self-Protected Output Drivers

Abstract: Lateral DMOS (LDMOS) power transistors of SMART technologies are widely used as output drivers in multiple applications. However, LDMOS devices are generally not robust under ESD due to deep snapback causing localized current crowding and leading to inhomogeneous triggering of the parasitic bipolar, ESD ruggedness of LDMOS power devices has been a significant subject in smart power IC technology. Lack of understanding in geometry scalability of the LDMOS devices often thwarts a proper implementation of self-protected structures. Therefore, it is necessary to understand the ESD scalability and failure mechanism of the power output devices to meet various levels of design requirement and optimize ESD protection solution. LDMOS devices ESD capability has been understood from snapback breakdown of the parasitic bipolar components. They usually show different behavior under ESD stress conditions, compared to the normal MOS transistors. The triggering mechanism of the snapback breakdown has been major subjects in terms of device structures and designs. In this paper, we report an ESD capability and scalability of the LDMOS devices from the geometry and operational aspects, employing both experimental and simulation data. Difference of transient electrical behaviors and failure mechanisms of DMOS with different geometries under ESD stress conditions is also addressed

A scaling law for the snapback in Superconducting accelerator magnets

Abstract: The decay of the sextupole component in the bending dipoles during injection and the subsequent snapback at the start of beam acceleration are issues of common concern for all superconducting colliders built or in construction. Recent studies performed on LHC and Tevatron dipole magnets revealed many similarities in the snapback characteristics. Some are expected, e.g. the effect of operational history. One particular similarity, however, is striking and is the subject of this paper. It appears that there is a simple linear relation between the amount of sextupole drift during the decay and the magnet current (or field) change during the ramp required to resolve the snapback. It is surprising that the linear correlation between snapback amplitude and snapback field holds very well for all magnets of the same family (e.g. Tevatron or LHC dipoles). In this paper we present the data collected to date and discuss a simple theory that explains the scaling found.

High voltage ESD-protection structure

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, eg, diode, in the ESD protection structure Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, eg, transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (eg, diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value) The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit

High speed lateral-IGBT with a passive gate

Abstract: A lateral-IGBT with a passive gate on collector portion has been proposed. Since the collector voltage directly drives the passive gate which controls the parasitic PNPTr, high-speed turn-off is compatible with low on-resistance without a side effect such as snapback I-V characteristics. Simulation results have shown drastic drop of fall time from 120ns to 5ns. Fabricated device have realize 6.8 ohm/mm/sup 2/ @ Kc=2V specific on-resistance, 780V blocking capability and improved turn-off characteristics similar to simulation results.

Dual direction ESD clamp based on snapback NMOS cell with embedded SCR

Abstract: In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.

Hybrid ESD clamp

Abstract: A circuit for protecting a semiconductor from electrostatic discharge events comprises a Zener diode (21) in series with a resistor (22) between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device (23) is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.

Snapback device studies using multilevel TLP and multi-impedance TLP testers

Abstract: Standard 50-ohm TDR TLP systems do not accurately measure the clamp voltage and minimum holding currents of snapback ESD protection structures. Two methods are presented that can accurately determine device operation at the turn-on point. Multilevel TLP generated with charge lines is contrasted with 100-to-1000-ohm TDRT for snapback parameter determination.

Device having a low-voltage trigger element

Abstract: An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.

Measurements of Field Decay and Snapback Effect on Tevatron Dipole and Quadrupole Magnets

Abstract: Since the beginning of 2002 an intensive measurement program has been performed at the Fermilab Magnet Test Facility (MTF) to understand dynamic effects in Tevatron magnets. Based on the results of this program a new correction algorithm was proposed to compensate for the decay of the sextupole field during the dwell at injection and for the subsequent field "snapback" during the first few seconds of the energy ramp. Beam studies showed that the new correction algorithm works better than the original one, and improves the Tevatron efficiency by at least 3%. The beam studies also indicated insufficient correction during the first 6s of the injection plateau where an unexpected discrepancy of 0.15 sextupole units of extra drift was observed. This paper reports on the most recent measurements of the Tevatron dipoles field at the beginning of the injection plateau. Results on the field decay and snapback in the Tevatron quadrupoles are also presented.

Simulation prediction of electrothermal behaviors of ESD N/PMOS devices

Abstract: This paper uses TCAD (technology computer-aided design) to calculate practical NMOS and PMOS device behaviors under ESD/EOS events The simulations include electrothermal effect with lattice temperature parameters These simulations reproduce TLPG (transmission line pulse generator) current–voltage curves successfully They also predict the same experimental tendencies of various device structural dimensions in practical engineering applications The electrothermal device simulation has shown its ability to predict a real device ESD/EOS event It will become a valuable tool to analyze device internal breakdown properties and find out optimized ESD/EOS conditions

Break-through of the trade-off between on-resistance and ESD endurance in LDMOS

Abstract: For the purpose of high ESD endurance and low on-resistance in LDMOS, we propose a new trench gate LDMOS. We call this structure HST-LDMOS (hard snapback trench gate LDMOS). In order to improve ESD endurance and on-resistance, the HST-LDMOS has P/sup +/ region between the driftN/sup -/ and N/sup +/ source and trench gate. Simulation results show that the HST-LDMOS achieves the ESD endurance of 16kV/mm/sup 2/ with the specific on-resistance of 6/spl square/6m/spl Omega/ mm/sup 2/. This is the best characteristic ever reported for the trade-off between on-resistance and ESD endurance. Furthermore, we presents the experimental on-resistance and snapback characteristics.

Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models

Abstract: A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only, mainly a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. It offers advantages of convenience in CAD implementation, high simulation speed, wider availability, and less convergence issues. The modeling approach has been used to investigate rise-time effects in TLP stress testing. The simulation, as well as measurement, demonstrated that the rising edge of TLP pulse affects snapback trigger voltage Vt1 not only in gate coupled NMOS but also grounded gate NMOS devices. It implies that the base transit time and the junction capacitance of parasitic BJT have impact on trigger voltage Vt1.

Mechanisms leading to erratic snapback behavior in bipolar junction transistors with base emitter shorted

Abstract: This paper discusses two different modes of breakdown in the reverse-biased I–V characteristics observed generically in bipolar junction transistors (BJTs) with the base emitter shorted, showing an erratic behavior, in the presence of large displacement currents. Experimental observations related to reverse-biased collector junctions of BJTs, that exhibit two different states of breakdown when a fast voltage ramp is applied are presented. Numerical simulations of the transient behavior of avalanche injection in p∕n−∕n+ structures show that two very close breakdown states coexist. The mechanisms leading to the erratic behavior of the second breakdown are discussed. The jittery nature of the breakdown is attributed to the delay associated with the buildup of the electric field across the n−∕n+ junction.

Method of evaluating semiconductor device

Abstract: The present invention provides a method of evaluating a semiconductor device having an ESD protective element, wherein a MOSFET is formed on the same substrate, comprising a step (electric characteristic measurement) for measuring an electric characteristic of the MOSFET, a step (snapback characteristic measurement) for measuring a snapback characteristic of the MOSFET, a step (impurity profile extraction) for extracting an impurity profile of the MOSFET from the electric characteristic and snapback characteristic of the MOSFET by using an inverse modeling technique, and a step (impurity profile adaptation) for causing the extracted impurity profile of the MOSFET and an impurity profile of the ESD protective element to correspond to each other, whereby the impurity profile of the ESD protective element is evaluated from the electric characteristic.

Cascode protected negative voltage switching

Abstract: A double cascode protected switchable voltage source may be used to selectively provide positive or negative voltage sources, for example, to a flash memory. The positive supply may be connected through a PMOS pass device to a first cascode protection device. A negative supply may be connected through an NMOS pass device and an NMOS cascode protection device to an output. The circuits may be designed so that exceeding snapback limits and gate aided drain breakdown are less likely.

Self protecting NLDMOS, DMOS and extended voltage NMOS devices

Abstract: In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an additional n-region next to the drain or an additional floating p-region next to the drain.

Dual mode negative voltage switching

Abstract: A negative switch may enable switching of two different negative voltages. The switch may include a negative cascode bias generator which biases the gate of a cascade protection device. When the negative switch is passing a large negative voltage, the bias generator generates a lowered voltage to provide a cascade voltage for snapback protection of a passing transistor. When a relatively low negative voltage is to be switched, the bias generator may produce a positive voltage greater than the threshold voltage of the cascode protection device so that both high and low negative voltages may be switched by the same circuit without exposing the passing device to a voltage in excess of its snapback limit.

Design and characterization of a novel high voltage power supply ESD protection

Abstract: The paper presents a high voltage power supply ESD protection element containing a high voltage VDMOS which is designed to survive bipolar snapback. For low currents, it operates as an "active clamp", and for high currents, the parasitic vertical bipolar transistor conducts the current. The snapback current level is higher than 250 mA for (transient) latch-up safety during normal operation.

Design and characterization of a high voltage SCR with high trigger current.

Abstract: This paper presents a novel type of high voltage SCR with high trigger current. For low currents the structure operates in ldquoactive clamprdquo mode and clamps the voltage to a value above the maximum operating voltage. After snapback the structure clamps the voltage to a low value as an SCR.

Fuse-type memory cells based on irreversible snapback device

Abstract: In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.

Esd protection element

Abstract: PROBLEM TO BE SOLVED: To lower and easily control the snapback voltage of a thyristor utilized as an ESD protection element. SOLUTION: The ESD protection element is composed of the thyristor, which interconnects an NPN transistor and a PNP transistor for protecting the internal element of a semiconductor device, and a trigger element which starts the operation of the thyristor when an overvoltage is impressed from an external connection terminal. The trigger element is composed of a plurality of MOS transistors diode-connected in series and has a gate and a drain of the post-stage MOS transistor coupled to the source of the pre-stage MOS transistor. The gate and the drain of the initial stage MOS transistor is coupled to an anode. The source of the final stage MOS transistor is coupled to the base of the NPN transistor. In the ESD protection element, the snapback voltage of the thyristor is decided by the sum of threshold voltages of a plurality of the MOS transistors. COPYRIGHT: (C)2005,JPO&NCIPI

Predictive simulation to improve reliability of a snapback-based NMOS clamp

Abstract: To incorporate high current electro-static discharge (ESD) conditions, we have extended a NMOS SPICE model to include models of a parasitic BJT, body (substrate) resistance and impact ionization current The approach taken models the geometry and layout dependence of the NMOS, making the model scalable The developed model predicts trigger voltages of MOS and BJT qualitatively and with reasonable accuracy Clamps having longer body to source spacing are seen to trigger the parasitic BJT faster, irrespective of the MOS channel length The parasitic BJT device parameters do not have significant effect on the clamp turn-on voltage