Showing papers on "Snapback published in 2006"

Theory of electrothermal behavior of bipolar transistors: part III-impact ionization

Abstract: A detailed theoretical and numerical analysis of single-finger and two-finger bipolar transistors is proposed, which includes both self-heating and impact-ionization effects. Although related to completely different physical phenomena, self-heating and impact ionization share a common feature in that they introduce a positive feedback mechanism that causes the same singularities in the current-voltage characteristics, namely, a snapback (or flyback) behavior and current bifurcation. These singularities are triggered if either one or both effects are activated. Based on a rigorous mathematical method, referred to as the "Jacobian method," generalized conditions are derived for determining the onset of flyback and bifurcation, which ultimately limit the safe operating region, as a result of the combined action of impact ionization and self-heating. The proposed formulation also includes several important effects not considered in previous contributions. Finally, a detailed analysis of the limiting boundaries for safe device operation is presented, and simple criteria for the optimal choice of the ballasting network are suggested

Circuit configurations to reduce snapback of a transient voltage suppressor

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.

Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS

Abstract: LDMOS transistors are widely used as output drivers in multiple applications in smart power IC designs. Relative to their sizes, LDMOS transistors are inherently weak with respect to ESD reliability and enhancing their ESD robustness has been an on-going challenge for many years. Snapback breakdown in MOSFET devices has been widely employed to explain the device failures due to ESD. A figure depicts a typical I-V characteristic and the testing device leakage evolution for a MOSFET device subject to transmission-line-pulse (TLP) ESD stress. For most conventional MOSFET devices, the first snapback breakdown, defined It1 and Vt1, is not a threat to the device until it reaches its thermal limit, It2. For most LDMOS cases, however, the first snapback breakdown can lead to the device damage. It has been broadly accepted that non-uniform snapback breakdown leads to current filamentation/crowding, which leads to excessive heating and failure. For a given type of LDMOS, two different failure modes are observed, which is dependent upon the effective gate width. A description and explanation of the different failure mechanisms due to these effects on the devices with different geometry is provided

Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced Smart Power technology

Abstract: A new approach, based on reduced and no-snapback components, was studied to face high-voltages I/Os severe ESD specifications An accurate physical analysis of the mechanisms encountered during ESD stresses drove to define the parameters controlling the snapback and the high current R ON , and then to quantify the attainable performances For the first time in Smart Power technologies, design rules are drawn to take full advantage of self-biased PNP for efficient high voltages protections TLP characterizations have confirmed the high potentialities of PNP

ESD protection design for mixed-power domains in 90nm CMOS with new efficient power clamp and GND current trigger (GCT) technique

Abstract: This paper presents an ESD protection design scheme for mixed-power domains in narrow ESD design window with ultra-thin gate oxides. Using a grounded gate (gg)NMOS-based clamp with contact ballast (CTB) layout technique, a factor of 3X area reduction can be achieved for MM protection of a 1.6 nm gate oxide compared to a conventional silicide-block ESD scheme. To expand the design window, a novel ground current trigger (GCT) technique using current sensing circuit between different GND busses is proposed. 7 kV HBM and 550 V MM can be achieved with a 2nd clamp with GCT technique, with the same area as a conventional snapback protection device. The GCT technique is also effective for SCR trigger element as cross clamp.

Turn-off characteristics of the CMOS snapback ESD protection devices - new insights and its implications

Abstract: The residual voltage across the ESD snapback protection device after its turn-off is one of the key parameters that must be considered for efficient ESD protection design. Turn-off characteristics of various snapback devices (5VNMOS, 5V LVTSCR and 12V DeMOS-SCR), are analyzed with experimental data for the first time and it is demonstrated that the residual voltage after turn-off is a unique parameter and depends on the type of ESD device, its architecture and layout. The residual voltage after turn-off can vary in a wide range from holding voltage to DC breakdown voltage and is a function of the ESD pulse amplitude. The underlying physical mechanism causing the waveform behavior is discussed in detail.

ESD protection circuit

Abstract: An ESD protection circuit includes a substrate, diode device, first snapback device, ring structure, second snapback device and a control circuit The diode device is formed in the substrate The first snapback device is formed in the substrate and includes a first heavy ion-doped region, a first gate and a second heavy ion-doped region The first heavy ion-doped region is coupled to the diode device The first gate is coupled to the second heavy ion-doped region The ring structure is formed in the substrate and includes a third heavy ion-doped region located The second gate is formed on the substrate between the second heavy ion-doped region and the third heavy ion-doped region to generate a second snapback device The control circuit is connected to the third heavy ion-doped region for preventing the turn-on of a parasitic SCR formed in the substrate in a normal operation

Negative voltage discharge scheme to improve snapback in a non-volatile memory

Abstract: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.

MOSFET ESD Breakdown Modeling and Parameter Extraction in Advanced CMOS Technologies

Abstract: This paper describes an approach for modeling the breakdown and snapback behavior of state-of-the-art MOSFET structures using equivalent-circuit description. Such models are required to enable circuit-level electrostatic discharge reliability simulations, which are a major challenge for the industry nowadays. Special attention is given to accurately describing the junction and gate leakage currents due to the increased tunneling generation in the scaled-down CMOS. Consistent parameter extraction procedures for the model parameters are described as well

Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions

Abstract: Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.

Compact Modeling of On-Chip ESD Protection Using Standard MOS and BJT Models

Abstract: SPICE type simulation using compact models is a very useful tool for predicting circuit performance under ESD stress conditions. However device models valid in the ESD current/voltage operating region are not widely available. This paper starts with a brief description of compact modeling for ESD devices working in snapback mode. A practical macro modeling approach for modeling snapback of MOS and LVSCR is then introduced. It uses advanced industry standard BJT and MOS models. This method's advantages are simplicity, high simulation speed, wider availability, and reduced convergence issues

High voltage ESD LDMOS-SCR with gate reference voltage

Abstract: In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.

Turn-On Voltage Control in BSCR and LDMOS-SCR by the Local Blocking Junction Connection

Abstract: The problem of local ESD protection of power arrays is addressed at the device level. A wide voltage range of the pulsed dV/dt turn-on is achieved using a local blocking junction connection. The approach is experimentally validated on both examples of Bipolar SCR and NLDMOS-SCR devices and implemented in a 0.5?m 24V BiCMOS process.

A new Principle for a Self-Protecting Power Transistor Array Design

Abstract: A new device level ESD protection solution for high-voltage NLDMOS power arrays is proposed and experimentally evaluated. Contrary to a conventional local clamp approach this new concept provides a self-protection capability within the array itself. The self-protecting capability of the NLDMOS array is achieved by embedding within some of the array fingers, a series of distributed diffusion regions that form an additional parasitic SCR structure with reversible snapback capabilities.

Concept for body coupling in SOI MOS transistors to improve multi-finger triggering

Abstract: Multi-finger SOI MOS devices exhibit a low ESD failure current, related to the thin Si-film and the complete isolation of the transistor body regions, causing non-uniform conduction in bipolar snapback mode. The traditional layout approaches (silicide blocked junctions, increased gate length) are compared and a novel layout concept is proposed to improve uniform triggering. Excellent ESD performance around 3mA/um2 is achieved for minimum dimension, fully silicided devices in a 90 nm SOI technology.

A Robust Novel Technique for SPICE Simulation of ESD Snapback Characteristic

Abstract: This paper presents a robust and novel technique for the circuit simulation of ESD (electrostatic discharge) snapback characteristic. A new linearization scheme for the avalanche current model in ESD evaluation shows a good convergence behavior during ESD stress simulation. This technique is compatible with the traditional circuit simulator based on the modified nodal analysis (MNA) like SPICE. We have implemented a simple ESD MOSFET model in SPICE3f5, and the simulation results are discussed

Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection

Abstract: The present invention relates to electrostatic discharge (ESD) protection circuitry Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers As a result, potential harm to the ESD protection device (eg, from current crowding) is mitigated and the effectiveness of the device is improved

Snapback by Hot Filament

Abstract: A simulation procedure using the conventional thermal-electric finite element method for the phase change memory has been developed. By introducing a defect on the amorphous chalcogenide of a reset phase change memory, the snapback by hot filament due to thermal runaway has been investigated by the numerical simulations with three-dimensional model.

New measurements of sextupole field decay and snapback effect on tevatron dipole magnets

Abstract: To perform detailed studies of the dynamic effects in superconducting accelerator magnets, a fast continuous harmonics measurement system based on the application of a digital signal processor (DSP) has been built at Fermilab. Using this new system, the dynamic effects in the sextupole field, such as the field decay during the dwell at injection and the rapid subsequent ''snapback'' during the first few seconds of the energy ramp, are evaluated for more than ten Tevatron dipoles from the spare pool. The results confirm the previously observed fast drift in the first several seconds of the sextupole decay and provide additional information on a scaling law for predicting snapback duration. The information presented here can be used for an optimization of the Tevatron and for future LHC operations.

Dual-direction Isolated NMOS-SCR device for system level ESD protection

Abstract: A novel dual-direction device is suggested for system level ESD protection. The device combines both a deep NWELL isolated snapback NMOS and a lateral SCR structure using a shared regions approach. ESD pulse operation of the device has been experimentally studied for a 0.35 mum 5 V CMOS process by numerical simulation and then experimentally validated for system level IEC specification requirements.

A Hall Plate Based Instrument to Measure the Snapback in the Large Hadron Collider Superconducting Dipole Magnets

Abstract: The decay and snapback of the magnetic field multipoles in superconducting particle accelerators like the Large Hadron Collider (LHC) could result in a significant particle beam loss unless adequately compensated. Whilst standard instrumentation used to measure the field quality of the superconducting magnets is good enough to measure the harmonic decay, it is not fast enough to measure the snapback. Therefore, a state of the art instrument was recently developed at CERN to measure the most important harmonics with a high measurement frequency and hence improve the understanding of the snapback phenomenon. In this paper we describe the instrument's principle of operation, its mechanical arrangement, its compensation system and its digital acquisition system. We also compare the performance of two different techniques implemented to achieve the necessary measurement resolution of 6 orders of magnitude lower than the main superimposed dipole field.

ESD clamp circuit between power supplies of high-voltage integrated circuits with latchup effect prevention

Abstract: The present invention discloses an ESD clamp circuit between power supplies of high-voltage integrated circuits with latchup effect prevention, which is applied on a high-voltage integrated circuit (IC) and is a stacked device composed of at least two high-voltage devices or one high-voltage device and at least one low-voltage device for operating on an ESD clamp circuit between power supplies such that a holding voltage exceeds a power supply voltage (VDD) under a snapback breakdown state Accordingly, the latchup effect issue encountered between high-voltage IC power supplies can thereby be avoided

Self-Protecting Arrays for Open Drain Circuits

Abstract: A new ESD protection strategy for NMOS arrays is described and experimentally evaluated. The problem of ESD protection of analog circuits has been addressed at the device/array level. Contrary to conventional rail-based or local clamp approaches this new concept provides for a self-protection capability into the array itself. The self-protecting capability of the NMOS array is achieved by embedding a local SCR region with reversible snapback capabilities and with a stronger dependence of the snapback voltage upon gate bias.

Antifuse programming circuit with snapback select transistor

Abstract: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Trade-off Characteristic between Gate Length Margin and Hot Carrier Lifetime by Considering ESD on NMOSFETs of Submicron Technology

Abstract: Hot carrier degradation and roll off characteristics of threshold voltage () on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control roll off down to the gate length margin. It was seen that the relationship between roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage () depends on drain current, and both and snapback holding voltage () depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

Programmable ESD protection structure

Abstract: In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.

Esd protection circuit for an integrated circuit with a negative voltage input terminal

Abstract: An ESD protection circuit is provided for protecting an integrated circuit from ESD damage and for protecting lightening surge. The ESD protection circuit includes a first snapback device and a second snapback device. The first snapback device is connected to a first terminal having a negative voltage of the integrated circuit during the operation of the integrated circuit. The first snapback device includes an anode coupled to the first terminal of the integrated circuit. The cathode of the first snapback device is coupled to a VCC terminal of the integrated circuit. The second snapback device has a cathode coupled to the VCC terminal. The anode of the second snapback device is connected to the ground of the integrated circuit. The snapback devices operate as silicon-controlled rectifiers (SCR) to protect the integrated circuit.